Xilinx
TM
HLS
Block Preview

Introduction

The block computes, in fixed-point arithmetic, $$ \mathrm{OUT} = -\mathrm{IN} $$ This is the time-multiplexed variant: the IN port carries TM samples packed side by side in one wide vector, and the same operation is applied to every slot in the same clock cycle. The scalar variant fixedp_neg is identical apart from the packing.

Every operand and every result carries its own Q format: the number of integer bits, the number of fractional bits and the sign are chosen independently. The binary point is tracked through the whole datapath, so operands with different scaling are aligned automatically – no manual shifting is required, which is the main practical difference with respect to the integer-only arithmetic blocks.

Pin Description

IN Input Variable bit TM
Time-multiplexed input operand. Width: (IN Integer Bits + IN Fractional Bits) x TM Factor.
Default: Must be connected
IN_DV Input 1 bit BIT
Input data valid, active high. Tie to ‘1’ for free running operation.
OUT Output 16 bit TM
Result, format Q(OUT Integer Bits . OUT Fractional Bits). Width: (OUT Integer Bits + OUT Fractional Bits) x TM Factor, packed like the inputs.
OUT_DV Output 1 bit BIT
Output data valid, asserted when the result is available.
NAN Output 1 bit BIT
Result undefined, asserted together with OUT_DV for the sample it qualifies. No operand makes this operation undefined, so this pin stays low here; it exists because every Fixed P. block presents the same status interface. NAN suppresses OL and UL. One bit for the whole TM word: the flag is the OR across the slots.
OL Output 1 bit BIT
Overflow: the true result left the OUT format and was saturated - wrapped instead, when Enable Saturation is NO. Asserted together with OUT_DV, mutually exclusive with UL, and suppressed by NAN. One bit for the whole TM word: the flag is the OR across the slots.
UL Output 1 bit BIT
Underflow: the true result was NOT zero but requantised to zero in the OUT format, i.e. the whole value was lost. Asserted together with OUT_DV, mutually exclusive with OL, and suppressed by NAN. One bit for the whole TM word: the flag is the OR across the slots.
CLK
Processing clock, connected to the acquisition clock.
RESET
Global synchronous reset, active high.

Properties

Property window

IN Integer Bits IN_BitsInt

Number of INTEGER bits of IN (the sign, when present, uses one of them).

Number of INTEGER bits of the operand IN (1 to 64). When the port is SIGNED one of these bits carries the sign.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

IN Fractional Bits IN_BitsFract

Number of FRACTIONAL bits of IN, i.e. how many bits sit to the right of the binary point. Total width = integer + fractional bits.

Number of FRACTIONAL bits of the operand IN (0 to 64), i.e. the bits to the right of the binary point. Total port width = integer + fractional bits.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

IN Sign IN_Sign

Select whether IN is a signed (two’s complement) or unsigned quantity.

Arithmetic type of IN:

  • SIGNED – two’s complement, range $[-2^{N_{int}-1}, 2^{N_{int}-1})$
  • UNSIGNED – non negative only, range $[0, 2^{N_{int}})$

Default: SIGNED

Options: UNSIGNED SIGNED

OUT Integer Bits OUT_BitsInt

Number of INTEGER bits of OUT (the sign, when present, uses one of them).

Number of INTEGER bits of the result OUT (1 to 64). When the port is SIGNED one of these bits carries the sign.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

OUT Fractional Bits OUT_BitsFract

Number of FRACTIONAL bits of OUT, i.e. how many bits sit to the right of the binary point. Total width = integer + fractional bits.

Number of FRACTIONAL bits of the result OUT (0 to 64), i.e. the bits to the right of the binary point. Total port width = integer + fractional bits.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

OUT Sign OUT_Sign

Select whether OUT is a signed (two’s complement) or unsigned quantity.

Arithmetic type of OUT:

  • SIGNED – two’s complement, range $[-2^{N_{int}-1}, 2^{N_{int}-1})$
  • UNSIGNED – non negative only, range $[0, 2^{N_{int}})$

Default: SIGNED

Options: UNSIGNED SIGNED

TM Factor TimeMultiplexing

Time multiplexing factor

Time multiplexing factor: 4, 8, 16 or 32 samples packed per port. One operator instance is generated per slot.

Default: 4

Options: 4 8 16 32

Rounding Rounding

ROUND: round to nearest when discarding fractional bits. TRUNCATE: drop them (cheaper, adds a DC bias).

  • ROUND – round to nearest when discarding fractional bits
  • TRUNCATE – discard them (cheaper, introduces a negative bias)

Default: ROUND

Options: TRUNCATE ROUND

Saturation EnableSaturation

YES: clip to the largest representable output value on overflow. NO: wrap around (cheaper, but overflow changes sign).

  • YES – clip to the largest representable output value on overflow
  • NO – wrap around modulo the output width

Default: YES

Options: NO YES

Status Flags StatusFlags

YES: the block exposes three extra 1-bit outputs, valid together with OUT_DV – NAN (the result is mathematically undefined for the operands presented, or the operand had to be clamped into the convergence domain of the algorithm), OL (overflow: the true result left the output format and was saturated), and UL (underflow: the true result was not zero but requantized to zero). NO: the pins are not generated and the logic that produces them is not synthesised.

Default: YES

Options: NO YES

Pipeline Length PipelineLength

Fixed latency of the block, in clock cycles. More stages ease timing closure. Ignored in SERIAL mode, where the latency is set by the iteration count.

Fixed latency of the block in clock cycles (1 to 8). Higher values ease timing closure without changing the numerical result.

Default: 2

Options: 1 2 3 4 5 6 7 8

Functional description

$$ \mathrm{OUT} = -\mathrm{IN} $$

where

  • IN – input operand, format $Q_{IN_BitsInt.IN_BitsFract}$
  • OUT – result, format $Q_{OUT_BitsInt.OUT_BitsFract}$

Fixed-point format

A value with $N_{int}$ integer bits and $N_{frac}$ fractional bits is stored on $N_{int} + N_{frac}$ bits and represents

$$ \text{value} = \frac{\text{raw integer}}{2^{N_{frac}}} $$

When the operand is SIGNED, one of the integer bits carries the sign (two’s complement). Each port is configured independently, so it is perfectly legal to feed a $Q_{16.0}$ signal and a $Q_{2.14}$ coefficient into the same block.

Implementation

Two’s complement negation with optional saturation on the most negative value.

Rounding and overflow

Two properties control how the internal full precision result is reduced to the output format:

  • Rounding – ROUND rounds to nearest when fractional bits are discarded, TRUNCATE simply drops them. Truncation is cheaper but introduces a systematic negative bias, which accumulates in a long processing chain.
  • Saturation – YES clips to the largest representable value, NO wraps around. Wrapping turns a small overflow into a full-scale sign flip, so saturation is strongly recommended for signal processing.

Time multiplexing

The wide ports carry TM samples packed from the least significant bits up:

    bits [W-1 : 0]      -> slot 0
  bits [2W-1 : W]     -> slot 1
  ...
  bits [TM*W-1 : (TM-1)*W] -> slot TM-1

where W is the width of a single sample. One operator instance is generated per slot, so the resource usage scales with the TM factor while the throughput stays one full set of samples per clock.

Latency

The PipelineLength property fixes the latency of the block in clock cycles (1 to 8). Raising it helps timing closure at high clock rates and does not change the numerical result. The symbol reports the configured latency.

Typical use cases

  • Polarity inversion of a detector signal
  • Building a subtractor out of an adder
  • Phase inversion in a signal chain