TM
Block Preview

Introduction

This block performs an AND reduction on a time-multiplexed (TM) input with configurable output mode.

TM mode: Reduces each phase separately. For each TM phase, the N-bit vector is reduced to a single bit. The output is TM with 1 bit per phase, and each bit is 1 only when all input bits in that phase are 1.

$$ \mathrm{OUT}[phase] = \bigwedge_{i=0}^{N-1} \mathrm{IN}[phase][i] $$

Full Reduce mode: Reduces all bits across all phases together. The output is a single bit (non-TM), which is 1 only when all input bits in all phases are 1.

$$ \mathrm{OUT} = \bigwedge_{phase=0}^{TM-1} \bigwedge_{i=0}^{N-1} \mathrm{IN}[phase][i] $$

where $\bigwedge$ denotes AND reduction over all bits.

Pin Description

IN_0 Input 16 bit TM
OUT Output 1 bit TM

Reduced output. Behavior depends on Output mode:

  • TM mode: TM output, width = 1 × TM Factor (1 bit per phase)
  • Full Reduce mode: Non-TM output, width = 1 (single bit)
IN Variable bit
Input data vector, always TM. Width: Input Size × TM Factor
Default: Must be connected

Properties

Property window

Input size (bits) InputSize

Set the size of each input in bits

Number of bits per input sample (per phase). Range: 1 – 16384.

Default: 16

Range: 1 – 16384

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Time-multiplexing factor. Range: 2 – 32.

Default: 4

Range: 2 – 32

Output mode OutputMode

TM: AND-reduce each phase separately (TM output). Full Reduce: AND-reduce all bits across all phases (single bit output)

Selects the output mode:

  • TM: AND-reduce each phase separately. Output is TM with 1 bit per phase.
  • Full Reduce: AND-reduce all bits across all phases. Output is a single bit (non-TM).

Default: TM

Options: TM Full Reduce

Functional description

TM mode

For each TM phase, the component performs:

$$ y[phase] = x[phase]_0 \land x[phase]1 \land \ldots \land x[phase]{N-1} $$

Output is 1 for a given phase if and only if all input bits in that phase are 1. The output has the same TM factor as the input (1 bit per phase).

Example: Input size = 8 bits, TM = 4

  • Input: 32 bits total (8 bits × 4 phases)
  • Output: 4 bits (1 bit per phase, TM)
  • Each output bit is the AND reduction of the corresponding 8 input bits

Full Reduce mode

The component performs AND reduction across all bits of all phases:

$$ y = x[0]_0 \land x[0]1 \land \ldots \land x[TM-1]{N-1} $$

Output is 1 if and only if all input bits across all phases are 1. The output is a single bit (non-TM).

Example: Input size = 8 bits, TM = 4

  • Input: 32 bits total (8 bits × 4 phases)
  • Output: 1 bit (single bit, non-TM)
  • Output bit is the AND reduction of all 32 input bits

Timing

Purely combinational with zero latency.

Typical use cases

  • TM mode: Checking if all bits in each phase are set (per-phase validation)
  • Full Reduce mode: Global valid/ready signal generation across all phases
  • Multi-bit status checking
  • Condition flags for control logic