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Introduction

This block implements a majority voting logic gate. It evaluates multiple single-bit inputs and produces a single-bit output based on the majority rule.

Operation:

  • Output = 1 if half or more of the inputs are 1
  • Output = 0 otherwise

The operation is purely combinational with zero clock latency. The number of inputs is configurable from 2 to 8 at component creation time.

For $N$ inputs with $M$ inputs at logic 1:

$$ \mathrm{OUT} = \begin{cases} 1 & \text{if } M \geq \lceil N/2 \rceil \ 0 & \text{otherwise} \end{cases} $$

Pin Description

IN_0 Input 1 bit BIT
IN_1 Input 1 bit BIT
IN_2 Input 1 bit BIT
OUT Output 1 bit BIT
Majority voting result (1 bit wide). Output is 1 if half or more inputs are 1, otherwise 0. Output is combinational (zero latency).
IN0, IN1, ..., IN(N-1) 1 bit
Input signals (single-bit each). Number of inputs: Configurable from 2 to 8 (set at creation time). Each input contributes one vote to the majority decision.
Default: Must be connected

Properties

Property window

Number of inputs InputSize

Set the number of input signals

Number of input signals for majority voting. Range: 2 to 8. This property is set during block creation and defines the voting threshold (ceiling of InputSize/2).

Default: 3

Range: 2 – 8

Functional description

The component implements majority voting logic in VHDL. It counts the number of active (1) inputs and compares it to the majority threshold:

$$ y = \begin{cases} 1 & \text{if } \sum_{i=0}^{N-1} x[i] \geq \lceil N/2 \rceil \ 0 & \text{otherwise} \end{cases} $$

where:

  • $x[i]$ → input bit $i$
  • $y$ → output bit
  • $N$ → total number of inputs (2-8)
  • $\lceil N/2 \rceil$ → majority threshold (ceiling of N/2)

Truth tables for common configurations

2-input majority (threshold = 1):

IN0 IN1 OUT
0 0 0
0 1 1
1 0 1
1 1 1

3-input majority (threshold = 2):

IN0 IN1 IN2 OUT
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Mathematical background

Majority voting is a fundamental concept in:

  • Fault tolerance: Triple modular redundancy (TMR) and higher
  • Noise rejection: Multiple sensor voting for reliability
  • Error correction: Majority logic decoding
  • Byzantine agreement: Distributed consensus algorithms

The majority function returns the most common value among the inputs, providing resilience against single-point failures or noise.

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Majority 0

The output changes immediately (after propagation delay) when any input changes.

Typical use cases

  • Triple modular redundancy (TMR) for fault tolerance
  • Multi-sensor voting for noise immunity
  • Redundant detector signal combination
  • Error detection and correction circuits
  • Safety-critical systems requiring redundancy