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Introduction

This block implements a simple dual-port RAM with separate read and write ports, allowing simultaneous access to different addresses. Read and write can operate on independent clock domains.

Read latency: 1 clock cycle.

Pin Description

IN Input Variable bit BIT
Input data for writing. Width: Bit Width.
Default: Must be connected
WRITE_ADDR Input 16 bit BIT VECTOR
Write address (16 bits). Range: 0 to Memory Size-1.
Default: Must be connected
WR Input 1 bit BIT
Write enable (1-bit). When 1, writes IN to WRITE_ADDR on CLK_WR edge.
Default: Must be connected
READ_ADDR Input 16 bit BIT VECTOR
Read address (16 bits). Range: 0 to Memory Size-1.
Default: Must be connected
CLK_RD Input 1 bit BIT
Read clock. Can be independent from CLK_WR.
Default: Must be connected
CLK_WR Input 1 bit BIT
Write clock. Can be independent from CLK_RD.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset.
Default: Must be connected
OUT Output Variable bit BIT
Output data from read. Width: Bit Width. Latency: 1 CLK_RD cycle.

Properties

Property window

Memory Size MemorySize

Set the amount of memory in number of words

Number of words. Allowed: 64-65536.

Default: 1024

Options: 64 128 256 512 1024 2048 4096 8192 16384 32756 65536

Bit Width BusWidth

Set the size in bits of the data

Bit width per word. Range: 1-1024.

Default: 1

Range: 1 – 1024

Functional description

Dual-port RAM has independent ports:

  • Write port: WRITE_ADDR, IN, WR, CLK_WR
  • Read port: READ_ADDR, OUT, CLK_RD

Can read and write simultaneously to different addresses, even with different clocks.

Timing

Write: Data written to WRITE_ADDR on CLK_WR rising edge when WR=1. Read: Data from READ_ADDR available 1 cycle after CLK_RD rising edge.

Typical use cases

  • Ping-pong buffers
  • Cross-clock-domain data storage
  • Producer-consumer queues