DSP - BLOCK RMS

Introduction link

The Block RMS block chops the input stream into consecutive blocks of N samples and, at the end of each block, publishes the root mean square of that block:

$$ S_2 = \sum_{i=0}^{N-1} x_i^2 , \qquad \mathrm{rms} = \sqrt{\frac{S_2}{N}} $$

One multiplier for $x^2$, one accumulator, one shift, one serial square root, one requantisation. That is the whole block.

N is a runtime input, not a property. You drive the exponent on the EXP pin and the block size is $N = 2^{\mathrm{EXP}}$:

Because N is a power of two, the division by N is an exact arithmetic shift. There is no divider and no reciprocal ROM, which is also why the block size can be changed while the design is running, for free.

What it is FOR link

The RMS is the amplitude of the block in the units of the input. It is the natural reading for a level meter, the error signal of an AGC loop, and the standard noise figure of a detector channel. Unlike the standard deviation it includes the DC level: a constant signal at level $c$ has an RMS of $|c|$ and a standard deviation of 0.

Two cheaper alternatives are worth knowing before you place this block:

• if the consumer only compares against a threshold, use Block Mean Square instead. The square root is monotone, so comparing $\overline{x^2}$ against the SQUARE of your threshold gives exactly the same decisions - and Block Mean Square has no root at all, a constant $L = 2$ tail, and no minimum usable exponent worth the name. Compare powers, square the threshold.
• if you only want a robust “how noisy is this” number, Block Mean Abs costs no multiplier and no root ($L = 2$) and, for a Gaussian signal, reads $\sqrt{2/\pi} = 0.7979$ times the standard deviation.

Take this block when the RMS number itself has to be reported, in input units, to a display, a log or a control loop.

When to use this instead of Block Statistics link

The all-in-one Block Statistics block is not deprecated and computes this same RMS among twenty other statistics. The rule is simple:

• you want several statistics of the SAME block - RMS and mean and min/max of the same N samples - use Block Statistics. They share one accumulator and one serial tail, so the second and third statistic are nearly free: the root engine that this block runs alone is the same one Block Statistics reuses for the standard deviation.
• you want exactly one number - use this block. Then you synthesise only that number: the pin list, the accumulator, the root and the tail are all that the RMS needs, and nothing else reaches the synthesiser.

Two Block Statistics blocks side by side would duplicate the accumulators; two per-operator blocks side by side duplicate them too. One Block Statistics block never does.

Pin Description link

Properties link

Accuracy link

The radicand is formed exactly. $S_2$ is an exact integer accumulator, the division by N is a shift, and the whole thing is pre-scaled by $2^{2 \cdot \mathrm{SQG}}$ with $\mathrm{SQG} = 4$ so that the digit recurrence delivers

$$ \mathrm{root} = \mathrm{rms}\cdot 2^{\mathrm{SQG}} = \sqrt{S_2 \cdot 2^{,2(\mathrm{RMS_{fract}}+\mathrm{SQG}) - 2,\mathrm{IN_{fract}} - \mathrm{EXP}}} $$

i.e. the root with 4 guard bits below the output LSB. The recurrence truncates and the final requantisation rounds, so the total error is bounded by

$$ |\mathrm{rms}{\mathrm{dut}} - \mathrm{rms}{\mathrm{exact}}| \le \frac{2}{16} + \frac{1}{2} < 1\ \mathrm{LSB} $$

and the host regression allows exactly 1 LSB - never more. There is no accumulated rounding, no truncated intermediate quotient and no approximation anywhere else in the datapath.

The pre-scaling shift saturates: a radicand that does not fit means the root does not fit either, which is precisely the output saturation you asked for with the Saturation property.

Accumulation and IN_DV link

IN_DV is the only qualifier. It says “this clock carries a sample”: a sample is squared, accumulated, and counts towards N, exactly on the clocks where IN_DV is high. Clocks with IN_DV low are ignored completely - whatever sits on IN during them cannot corrupt the block - while the serial tail keeps running, which is what you want: the tail has nothing to do with the input stream.

Unconnected, IN_DV ties to '1' and EXP ties to 10 (N = 1024), so the block free-runs with nothing wired except IN.

There is deliberately no CE pin. On the all-in-one Block Statistics block an earlier revision had one, and it did not survive synthesis: with nothing but internal state gated by it, Vitis could reason the frozen path away and delete the port from the generated entity while SciCompiler’s wrapper still wired it, which failed a real Vivado build with [VRFC 10-718] formal port <ce> does not exist in entity. The whole per-operator family was built without one. To stall this block, gate its IN_DV - a block that only accumulates on IN_DV has no need to be frozen, and there is no reason to stall the tail.

When EXP changes link

EXP is clamped to Max Block Exponent and then latched on the first accepted sample of a block, and held for that whole block. A change therefore takes effect on the NEXT block: a block in progress always finishes against the N it was started with, and a block is never emitted against a different N than the one it was accumulated with. You can sweep EXP from a register interface while the stream runs and every result stays self-consistent.

Timing: the serial tail link

Why it is serial link

A block has a whole block period of slack after its N-th sample: the next result is not due for another $2^{\mathrm{EXP}}$ clocks. So there is no reason to build a parallel datapath for the post-accumulation arithmetic. II=1 is only needed while ACCUMULATING - one sample per clock, one multiply, one add - and the tail has all the time in the world.

The square root is therefore ONE reused compare-subtract stage stepped once per clock, producing one result bit per clock, instead of an unrolled digit recurrence costing RTW comparators. The cost is CLOCKS, not comparators, and there is no DSP in the tail - the only multiplier in the block is the $x \cdot x$ during accumulation.

A direct consequence: a wide RMS format costs clocks, not gates.

The latency contract link

OUT_DV pulses for one clock when the tail COMPLETES, L clocks after the clock on which the N-th sample of the block was accepted - not when that sample arrives. RMS is updated on that same clock and on no other. The state walk is IDLE -(go)-> LD -> SQRT x RTW -> FIN -> IDLE with OUT_DV registered, so

$$ \mathrm{RTW} = \mathrm{RMS\ width} + \mathrm{SQG} + 1 = \mathrm{RMS\ width} + 5, \qquad L = 2 + (\mathrm{RTW} + 1) $$

L depends only on the RMS output width. It does not depend on the input width, and - unlike Block Variance and Block Std Dev - it does not depend on EXP either: this block’s tail is a constant for a given configuration.

The 2^EXP >= L rule link

The tail of one block must finish before the next block completes:

$$ 2^{\mathrm{EXP}} \ge L $$

If a block completes while the previous tail is still running, that block’s result is DROPPED. A completed block is only handed to the tail when the tail is IDLE, so: no OUT_DV for it, the accumulator is unaffected, later blocks come out correctly - and there is no error pin. A result is simply skipped.

Three things guard against it, and one hole remains:

• the property validator refuses a configuration whose minimum exponent exceeds Max Block Exponent, and tells you the tail length and the minimum;
• CompileHDL prints the tail length and the minimum usable EXP into the compilation log for every placement;
• but EXP is a PIN. Nothing can stop a user driving it below the minimum at RUN TIME. If you make EXP runtime programmable from a register interface, clamp it in your own logic - the block will not complain, it will just stop emitting some results.

Worked numbers link

Take the first row in full. An 8 bit signed input with the default RMS format (16 integer bits, 0 fractional bits, unsigned) gives $\mathrm{RTW} = 16 + 5 = 21$ and $L = 2 + 21 + 1 = \mathbf{24}$ clocks. The smallest exponent with $2^{\mathrm{EXP}} \ge 24$ is $\mathrm{EXP} = 5$ ($2^5 = 32 \ge 24$; $2^4 = 16 < 24$), so the minimum usable EXP is 5, a block of 32 samples. Every row is computed the same way - and note that the input width never enters the formula.

Knowing where the block is: BUSY, INTEGRATING and SAMPLE_COUNT link

Three optional status outputs, all defaulting to NO. They answer different questions:

Every output of this block is a register, so each status bit is observed on the clock after the event that sets it:

• INTEGRATING rises on the clock after the FIRST sample of a block is accepted and falls on the clock after the N-th - it is high exactly while the block is ACCUMULATING, and never during the tail.
• BUSY covers the accumulation and the serial tail. It rises with INTEGRATING, stays high across the tail, and its LAST HIGH CLOCK IS THE OUT_DV PULSE; it falls on the clock after. BUSY high with INTEGRATING low therefore means “the samples are all in, I am computing”.
• On a continuous stream the next block starts before the previous tail ends, so BUSY never drops and INTEGRATING dips for exactly one clock per block boundary - which makes it a free block marker. The two separate visibly only when the input pauses for longer than the tail.
• SAMPLE_COUNT is a fixed 32 bits and reads 1 after the first accepted sample, N after the N-th. It is NOT cleared at the block end: it HOLDS the final count N through the whole tail and past OUT_DV, until the first sample of the next block takes it back to 1. So on the OUT_DV clock it reads the length of the block being presented - which is the useful thing to latch alongside the result. Only RESET clears it to 0.

Q formats link

Both data ports carry their own fixed point format (integer bits, fractional bits, sign), the same convention as the Fixed P. family. The result is requantised into the RMS format with the selected rounding (nearest / truncate) and overflow policy (saturate / wrap); saturation is symmetric for signed formats, as everywhere else in the toolchain.

Sizing: the RMS is in the units of the input and can never exceed the largest magnitude in the block, so the input integer bits are always enough. An RMS is never negative, so UNSIGNED buys one bit - which is the default. The total RMS width is what sizes the serial root ($\mathrm{RTW} = \mathrm{width} + 5$ steps), so ask for fractional bits when you want sub-LSB amplitude resolution, but do not make the format wider than you need: every extra bit is one more clock of tail and one step closer to the minimum usable exponent.

Cost link

One multiplier for $x^2$ (unavoidable at one sample per clock), one accumulator ($2\cdot\mathrm{IN_SW} - 1 + $ Max Block Exponent bits), one barrel shifter for the pre-scaling, one compare-subtract stage with a radicand, a remainder and a root register, and one requantiser. No divider, no second multiplier and no DSP in the tail.

Verification link

The core is regression tested by a host-side csim harness (tb/block-ops/run_tb.ps1) that runs one simulated clock at a time and follows OUT_DV. The expected values come from tb/block-ops/gen_golden.py, which evaluates $\sqrt{S_2/N}$ in exact rational arithmetic and shares no algorithm with the core; the tolerance is 1 LSB and not one count more. RMS coverage includes pseudo-random, sine, all-zero and constant inputs, a fractional output format, truncate instead of round, IN_DV gaps inside the accumulation, an EXP that alternates between blocks, and a burst input that stops for longer than the 24-clock tail so that BUSY and INTEGRATING are separated for the whole of it. The status outputs are checked clock by clock against the contract above. A cross-check compiles this core and the all-in-one block_stats.cpp into the same binary, drives them with identical stimulus, and compares the two clock by clock; tb/block-ops/port_check.py preprocesses the real core to prove the symbol’s pin list matches the entity’s port list for every enable combination, and the harness #errors at COMPILE TIME if the tail formula in the .cpp, in the plugin and in the generator ever disagree.