Xilinx
Block Preview

Introduction

The block produces a stream of uniformly distributed pseudo-random words: a new word on every clock where CE is high (DV marks it). The output is the top OUT bits of a 64-bit generator word, so the same stream is uniform whether you read it as unsigned $[0, 2^W-1]$ or as two’s complement $[-2^{W-1}, 2^{W-1}-1]$ — the bit pattern is format agnostic.

Three generator cores are available, all pure logic (shift, XOR, add — no DSP, no BRAM):

  • XOSHIRO256** (recommended) — Blackman/Vigna xoshiro256**. Period $2^{256}-1$, passes the modern statistical test suites (the multiplications by 5 and 9 are implemented as shift-adds). This is the “whitest” option: use it whenever statistical quality matters (noise floors, Monte-Carlo stimuli, dithering).
  • Tausworthe LFSR258 — L’Ecuyer’s 5-component combined Tausworthe, 64 bit, period $\approx 2^{258}$, maximally equidistributed. The classic FPGA generator family (the Gaussian Noise block uses a 32-bit sibling internally).
  • XorShift64 — Marsaglia’s 13/7/17 xorshift, period $2^{64}-1$, a single 64-bit register: the smallest option. Being one linear recurrence it fails linear-complexity style tests — fine as a cheap generic stimulus, prefer xoshiro for measurements.

Seeding and reproducibility

The 128-bit SEED property is randomized automatically when the block is placed, so several generators in one design are decorrelated out of the box. The seed is expanded to the full generator state (up to 5 x 64 bit) with SplitMix64 — the canonical seeding procedure — and degenerate states are sanitized automatically. Set two instances to the same seed to get two identical streams; RESET reloads the seed, so the sequence restarts from the beginning and simulations are deterministic.

What a seed has to look like

Any string of exactly 32 hexadecimal digits is a valid seed, with no exceptions and no values to avoid:

  • all 32 digits may be the same (FFFF...FFFF);
  • the seed may be all zeros;
  • the two 64-bit halves may be identical (DEADBEEFDEADBEEF written twice), and the two halves may be swapped — every one of those is a distinct, fully usable generator state.

A seed that is not exactly 32 hexadecimal digits is reported as a compile error; nothing else about a seed is ever repaired silently.

Two seeds that differ in only ONE of their two 64-bit halves — which includes every pair differing by a single digit — are guaranteed to produce different generator states; for any other pair the probability of a collision is negligible. So two instances of this block, or of any block of the noise family (they share this seeding code), are independent as soon as their seeds differ at all. That is the property to rely on in a multichannel design.

Changed in this version. The seed expansion was corrected (the two internal SplitMix64 streams are now started at different offsets). Two consequences: seeds whose halves are equal, or merely swapped, are no longer collapsed onto one shared state — and the state produced by any given seed is different from the one produced by earlier versions. A design recompiled with this release therefore gets a different, equally reproducible pseudo-random stream from the same seed.

Pin Description

CE Input 1 bit BIT
Clock enable, active high: a new random word is produced on every clock where CE is high. Default when unconnected: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock. Rising edges drive all operations.
Default: Default Board Clock
RESET Input 1 bit BIT
Restarts the sequence from the seed (the stream repeats identically after every reset).
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
The random word, OutputBits wide (top bits of the 64-bit generator word). Uniform as unsigned or as two’s complement.
DV_OUT Output 1 bit BIT
High on every clock that carries a new word (follows CE).

Properties

Property window

Algorithm Algorithm

Pseudo-random generator core. XOSHIRO256** (recommended): period 2^256-1, best statistical quality, no DSP. Tausworthe LFSR258: period ~2^258, the classic FPGA combined Tausworthe. XorShift64 (smallest): period 2^64-1, one 64-bit register, cheapest - fine as a simple stimulus.

  • XOSHIRO256** (recommended): period 2^256-1, best statistical quality, no DSP.
  • Tausworthe LFSR258: period ~2^258, the classic FPGA combined Tausworthe.
  • XorShift64 (smallest): period 2^64-1, one 64-bit register - cheapest, fine as a simple stimulus.

Default: XOSHIRO256** (recommended)

Options: XOSHIRO256** (recommended) Tausworthe LFSR258 XorShift64 (smallest)

Output bits OutputBits

Width of the OUT word (2..64): the top bits of the 64-bit generator word. Uniform whether read as unsigned [0 .. 2^W-1] or two’s complement [-2^(W-1) .. 2^(W-1)-1].

Width of OUT (2..64): the top bits of the generator word.

Default: 16

Range: 2 – 64

SEED (32 digit hex) SEED

Generator seed (128 bit, 32 hex digits), expanded internally to the full generator state with SplitMix64. Automatically randomized when the component is created, so multiple instances produce independent streams; set two instances to the same seed to get identical streams. RESET restarts the sequence from the seed.

128-bit seed as 32 hex digits. Auto-randomized when the component is created (independent instances); editable for reproducible streams. Expanded internally to the full generator state with SplitMix64. Every string of exactly 32 hex digits is a valid seed - repeated digits, all zeros and two identical 64-bit halves included; a wrong length or a non-hex digit is a compile error. Two seeds that differ in one half are guaranteed to give two independent streams.

Default: F351AB1756984BECB7CBCD00DFB87CDE

Usage notes

  • Leaving CE unconnected ties it to ‘1’: one word every clock.
  • For a bipolar noise source just treat OUT as signed: the stream is already symmetric around zero. For unipolar, treat it as unsigned.
  • A 1-bit output (OutputBits can be dropped by taking fewer bits downstream) gives an unbiased random bit stream.
  • Chain the output into the Shapers IIR filters to spectrally shape the noise; the stream is white (flat) at the full clock rate.

Verification

Each algorithm is checked bit-exactly against an independent Python reference implementation (golden vectors, first words after reset), plus CE gating, reset-restart, output slicing and a statistical smoke test (per-bit balance over 4096 words, no repeated consecutive words) in a self-checking GHDL regression; mutation-tested (a wrong rotation, tap or mask in any of the three cores makes its scenario fail).