Xilinx
TM
Block Preview

Introduction

This block implements a time-multiplexed FIFO that buffers TM data streams. All TM phases are processed through the same FIFO logic.

Pin Description

IN Input Variable bit TM
TM input data. Width: Bit Width × TM Factor.
Default: Must be connected
WR Input 1 bit BIT
Write enable.
Default: Must be connected
RD Input 1 bit BIT
Read enable.
Default: Must be connected
CLK_RD Input 1 bit BIT
Read clock.
Default: Must be connected
CLK_WR Input 1 bit BIT
Write clock.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset.
Default: Must be connected
OUT Output Variable bit TM
TM output data. Width: Bit Width × TM Factor.
EMPTY Output 1 bit BIT
Empty flag.
FULL Output 1 bit BIT
Full flag.
PROG_EMPTY Output 1 bit BIT
PROG_FULL Output 1 bit BIT
OVERFLOW Output 1 bit BIT
UNDERRUN Output 1 bit BIT

Properties

Property window

FIFO depth MemorySize

Set the amount of memory in number of words

FIFO depth. Allowed: 64-65536.

Default: 1024

Options: 64 128 256 512 1024 2048 4096 8192 16384 32756 65536

Bit Width BusWidth

Set the size in bits of the data (per phase)

Bit width per TM phase (not total).

Default: 16

Range: 1 – 1024

TM Factor TMFactor

Time Multiplexing factor (number of phases)

TM factor. Total width = BusWidth × TMFactor.

Default: 4

Range: 2 – 32

Prog Empty ProgEmpty

Set PROG_EMPTY threshold in word. MUST BE BETWEEN 3 AND FIFO SIZE -3!

Default: 3

Range: 3 – 65535

Prog Full ProgFull

Set PROG_FULL threshold in word. MUST BE AT MAXIMUM FIFO SIZE - 3!

Default: 1021

Range: 1 – 65535

Functional description

TM FIFO operates similarly to standard FIFO but handles TM-wide data vectors. Each FIFO entry stores an entire TM vector (all phases).

Refer to standard FIFO documentation for operational details.