HLS
Block Preview

Introduction

The Rise Time block computes the elapsed time a unipolar pulse needs to rise from a lower percentage of its maximum amplitude to a higher one.
Operation sequence:

  1. Trigger – a rising edge on TRIGGER arms the state machine.
  2. Peak search – within WINDOW samples the maximum value PEAK is detected while the incoming stream is delayed by WINDOW + PRE_TRIGGER samples.
  3. Threshold generation – absolute thresholds
    $$V_{thr1} = \frac{THRS_1}{2^{16}};PEAK ,\qquad V_{thr2} = \frac{THRS_2}{2^{16}};PEAK$$ are computed.
  4. Timestamp extraction – the delayed waveform is scanned until it crosses the two thresholds, providing TIME_1 and TIME_2.
  5. Result – RISETIME = TIME_2 - TIME_1 together with TIME_PEAK, PEAK and a one-cycle strobe DV.

Pin Description

DATA_IN Input variable bit BIT VECTOR
Unsigned sample stream from the ADC. Width equals BIT_SIZE (16 bit). One sample is processed per clock.
Default: Must be connected
BASELINE Input variable bit BIT VECTOR
Offset value to be subtracted from DATA_IN. Use a running average or a constant pedestal to centre the waveform around zero.
Default: 0
TRIGGER Input 1 bit BIT
Active-high strobe starting a new measurement. Only the rising edge is detected; the signal may be de-asserted immediately.
Default: Must be connected
THRS_1 Input variable bit BIT VECTOR
Lower percentage threshold coefficient ($0-65535$ → 0 %–100 % for 16 bit input size).
Typical value for 10 % is 0x199A.
Default: 0
THRS_2 Input variable bit BIT VECTOR
Upper percentage threshold coefficient. 90 % corresponds to 0xE666 for 16 bit input size.
Default: 0
WINDOW Input 16 bit BIT VECTOR
Peak-search window length in clock cycles. Also defines the maximum observation time after threshold crossings.
Default: 0
PRE_TRIGGER Input 16 bit BIT VECTOR
Additional delay (samples) applied to the waveform so that pre-trigger information is available during analysis.
Default: 0
CLK Input 1 bit BIT
System clock. All inputs and outputs are synchronous to its rising edge.
Default: Default Board Clock
RESET Input 1 bit BIT
Asynchronous active-high reset. Clears internal state machines and memories; outputs are invalid while asserted.
Default: Default Board Reset
RISETIME Output 16 bit BIT VECTOR
Measured rise-time
$$RISETIME = TIME_2 - TIME_1$$
Units: clock cycles (×1/16 when interpolation is enabled).
TIME_1 Output 16 bit BIT VECTOR
Timestamp at which DATA_IN crossed THRS_1. Same resolution as RISETIME.
TIME_2 Output 16 bit BIT VECTOR
Timestamp at which DATA_IN crossed THRS_2.
TIME_PEAK Output 16 bit BIT VECTOR
Timestamp of the maximum amplitude within the peak-search window.
DV Output variable bit BIT
Data-valid pulse. Asserted for one clock when RISETIME, TIME_* and PEAK are stable.
PEAK Output variable bit BIT VECTOR
Maximum amplitude (baseline-corrected) detected inside the window.
DATA_OUT Output variable bit BIT VECTOR
Real-time baseline-corrected stream y[n]. Primarily for debugging or downstream processing.

Properties

Property window

Input Data Size BIT_SIZE

Width of the data path. Only 16 bit is supported: the HLS core keeps the peak and the two absolute thresholds in 16-bit registers (risetime.cpp:44-48), so a wider data path would wrap them silently. The 32 bit option was WITHDRAWN - see AGENT/SOLVED.md #20.

Width of the data path. 16 bit is the only supported value.

A 32 bit option used to be offered and has been withdrawn: the core keeps the running peak and the two absolute thresholds in 16 bit registers and their products in 32 bit ones, so a wider data path truncated the peak and overflowed the threshold multiplication, giving wrapped thresholds and wrong times with no error reported. The core was not widened, so the setting is now refused both in this window and at compile time; a project saved with 32 bit stops generating HDL with a message telling you to lower the value.

All amplitudes (DATA_IN, BASELINE, THRS_1, THRS_2, PEAK, DATA_OUT) are therefore 16 bit wide.

Default: 16

Options: 16

Enable Interpolation EN_INTERPOLATION
Enables 4-bit linear interpolation, improving timing resolution from 1 sample to 1/16 sample. Requires two extra DSP blocks and a few LUTs.

Default: False

Maximum Buffer Length MAX_RISE_LEN
Size of the circular buffer (samples). Must satisfy
MAX_RISE_LEN ≥ WINDOW + PRE_TRIGGER.

Default: 1024

Options: 1024 2048

Functional overview

Let $x[n]$ be the input sample stream and $B$ the baseline.
The block first produces the baseline-corrected waveform

$$ y[n] = \max\bigl(0,;x[n] - B\bigr) $$

which is written into a circular buffer of depth MAX_RISE_LEN. A delayed copy

$$ y_d[n] = y\bigl[n-(WINDOW+PRE_TRIGGER)\bigr] $$

is used for threshold comparison so that the timestamps refer to the original trigger instant.

After a trigger, the peak value is searched for WINDOW clock cycles:

$$ PEAK = \max_{0 \le k < WINDOW};y[n_0+k] $$

Absolute thresholds are then generated from the user-defined 16-bit fixed point coefficients THRS_1 and THRS_2 (0 → 0 %, 65535 → 100 %). The delayed waveform is scanned further until

$$ y_d[n_1] \ge V_{thr1},\qquad y_d[n_2] \ge V_{thr2},\qquad n_1 < n_2 $$

yielding

$$ TIME_1 = n_1,\quad TIME_2 = n_2,\quad RISETIME = n_2 - n_1 $$

Risetime measurement

Optional interpolation

When EN_INTERPOLATION is true, a 4-bit linear interpolation refines the crossing times giving a resolution of one sixteenth of a sample:

$$ \Delta n = \frac{V_{thr}-y_{prev}}{y_{curr}-y_{prev}};;,\qquad TIME_{INTP}= (n \ll 4) + \left\lfloor 16 ;\Delta n \right\rfloor $$

Interpolation

Timing

Clock to clock latency of the data path DATA_IN → DATA_OUT is 1 cycle (pipeline register).
Latency from the trigger edge to a valid result (DV = '1') is

$$ L \approx PRE_TRIGGER + 2\cdot WINDOW + 6;\text{cycles} $$

The formula covers the peak search, threshold calculation and final scanning phases. Worst-case latency is obtained when WINDOW equals its maximum value.

For a 125 MS/s digitizer (4 ns/sample) and settings
THRS_1 = 0.1·2^16, THRS_2 = 0.9·2^16, WINDOW = 128, PRE_TRIGGER = 32:

$$ RISETIME = 7;\text{samples} ; \Rightarrow ; 56;\text{ns} $$

Example – n/γ discrimination with a ³He proportional counter (125 MS/s)

Theory in brief
In a ³He proportional tube, neutron capture (n + ³He → p + ³H + 764 keV) releases two heavy charged particles that deposit energy along a several-cm track. The resulting current pulse has a fast electron component (tens of ns) and a slow ion component (hundreds of ns–µs). After the charge-sensitive preamplifier (≈ RC integration), the output can be modeled as the sum of two exponentials:

[ v(t)=A_f\left(1-e^{-t/\tau_f}\right)+A_s\left(1-e^{-t/\tau_s}\right),\quad \tau_f \ll \tau_s ]

For γ interactions (mainly Compton electrons), (A_s) is small and the pulse is dominated by the fast term → shorter 10–90 % rise time. For neutrons, the slow ion term contributes significantly, stretching the leading edge → longer rise time. Measuring

[ RISETIME = t_{90%}-t_{10%} ]

therefore discriminates n/γ. (If only one exponential is present, (t_{p%}=-\tau \ln(1-p)) and (RISETIME\approx 2.2,\tau); the presence of a second slow component effectively increases the measured rise time.)