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Introduction

The TRP NEW block implements the same dual trapezoidal-filter chain as TRP MCA (fast trigger filter + slow energy filter for transistor-reset pre-amplifiers) and supersedes it. The improvements come from a systematic investigation on real 2 Mcps SDD data:

  • Trigger validation window widened to (TRIG_K + TRIG_M)·2 samples (the legacy TRIG_K·2 window expired before the zero crossing when the detector rise time exceeded a few samples: up to ~45 % of the pulses produced no trigger at all, and their un-vetoed trapezoids corrupted the baseline average, producing rate-dependent ghost peaks that grew with the baseline length).
  • Leakage correction on the energy path: the LEAKAGE_M / LEAKAGE_Q ramp is now subtracted from the signal that feeds the energy trapezoid (in TRP MCA it only drove the LEAKAGE SIG monitor output).
  • Baseline pre-guard (BL PRE GUARD pin): the baseline average can be stopped a programmable number of samples before each trigger, so the rising edge of the pulse never enters the average.
  • Statistics block: input/output/reset/lost/pileup counters and windowed ICR/OCR rate meters, with a synchronous RESET STAT clear.
  • Optional pileup rejector (compile-time property): discards both events of a too-close pair or only the second event riding on the tail of the first. Decisions are taken at the energy sampling point, so no output is delayed and the block latency does not change.

With ENABLE_PILEUP_REJECTOR = False and the new input pins left unconnected the block behaves exactly like TRP MCA except for the wider (correct) trigger validation window.

Pin Description

DATA_IN Input ADC_BITS_N bit BIT VECTOR
Unsigned ADC sample bus (LSB = 1 count). Width configured through property ADC_BITS_N (default 24 bit).
Default: Must be connected
POLARITY Input 1 bit BIT
1 = pulses are positive; 0 = pulses are negative. Selects internal inversion path.
Default: 1
OFFSET Input ADC_BITS_N+1 bit BIT VECTOR
Two’s-complement digital offset added after polarity inversion. Used to shift the staircase towards mid-code.
Default: 0
THRS Input 32 bit BIT VECTOR
Signed trigger threshold expressed in delta units of the trigger trapezoid.
Default: 256
TRIG_K Input 16 bit BIT VECTOR
Peaking length k (samples) for the trigger trapezoid. Choose it comparable to the input rise time. Minimum 3 (a lower value is used as 3).
Default: 6
TRIG_M Input 16 bit BIT VECTOR
Gap length m (samples) for the trigger trapezoid. Minimum 3 (a lower value is used as 3).
Default: 8
TRAP_K Input 16 bit BIT VECTOR
Peaking length k (samples) for the energy trapezoid. Minimum 2 (a lower value is used as 2).
Default: 256
TRAP_M Input 16 bit BIT VECTOR
Gap length m (samples) for the energy trapezoid. Flat top = TRAP_M − TRAP_K samples. Minimum 2 (a lower value is used as 2).
Default: 266
TRAP_GAIN Input 24 bit BIT VECTOR
Post-filter gain $G$ coded as Q8.16 (default unity = 0x010000).
Default: 65536
BL_LEN Input 4 bit BIT VECTOR
Baseline average depth exponent. Actual length = 2^BL_LEN samples. 0 disables the baseline restorer.
Default: 8
BL_INIB Input 16 bit BIT VECTOR
Samples of baseline inhibition after every trigger. Must cover the whole trapezoid, ≥ 2·TRAP_K + TRAP_M + BL_PRE_GUARD.
Default: 4096
BL_PRE_GUARD Input 8 bit BIT VECTOR
New. The baseline average is stopped this many samples BEFORE each trigger (delay-line pre-guard). 0 = legacy behaviour. Upper bound set by the BL_PRE_GUARD_MAX property. Remember to enlarge BL_INIB accordingly. Minimum 4: a lower value is used as 4.
Default: 0
SAMPLE_POS Input 16 bit BIT VECTOR
Delay between trigger validation and energy sampling (samples). Centre it on the flat top, ≈ TRAP_K + (TRAP_M − TRAP_K)/2. Minimum 1 (a lower value is used as 1).
Default: 264
LEAKAGE_M Input 24 bit BIT VECTOR
Leakage-ramp increment per clock (signed, Q4.20 = ADC counts per sample × 2^20). In TRP NEW the correction is applied to the ENERGY trapezoid input, not only to the LEAKAGE SIG monitor. 0 = off.
Default: 0
LEAKAGE_Q Input 24 bit BIT VECTOR
Initial leakage accumulator value reloaded at every reset (signed Q4.20).
Default: 0
ENABLE_EXTERNAL_RESET Input 1 bit BIT
1 = use pin TR_RESET; 0 = use automatic reset detector.
Default: 0
HIGH_RATE_MODE Input 1 bit BIT
Static configuration (defaults to 0 when unconnected). With it high the post-reset trigger inhibition preroll is zero, so triggering resumes as soon as the reset guard expires: fewer events lost at high rate, at the cost of accepting triggers while the baseline is still recovering.
Default: 0
TR_RESET_THRESHOLD Input ADC_BITS_N bit BIT VECTOR
Amplitude of the 4-sample drop that declares a pre-amplifier reset (automatic detector).
Default: 0
TR_RESET_GUARD Input 16 bit BIT VECTOR
Duration (samples) of the veto after a reset. Must cover the energy-trapezoid recovery, ≥ TRAP_K + TRAP_M + TR_RESET_PRE_GUARD + margin — a shorter guard lets the negative recovery pollute the baseline (left tail in the baseline histogram, see the Reset veto and guard sizing section).
Default: 0
TR_RESET_PRE_GUARD Input 16 bit BIT VECTOR
Input delay applied before reset detection, letting the veto anticipate the reset transient (bounded by the TR_RESET_DELAY property). Minimum 2 (a lower value is used as 2).
Default: 0
RESET_STAT Input 1 bit BIT
New. Synchronous clear (active-high level) of every statistics counter and rate meter.
Default: 0
STAT_WINDOW Input 32 bit BIT VECTOR
New. ICR/OCR integration window in clock cycles. Set = clock frequency to read counts per second. 0 disables the rate meters.
Default: 0
PILEUP_DIST_BOTH Input 16 bit BIT VECTOR
New. Pileup rule 1: if the distance between two triggers is below this value BOTH events are discarded. 0 = rule off. Clamped to SAMPLE_POS at runtime (see How the two rules are evaluated).
Default: 0
PILEUP_DIST_GUARD Input 16 bit BIT VECTOR
New. Pileup rule 2: if the distance is between PILEUP_DIST_BOTH and this value only the SECOND event is discarded. 0 = rule off. Unbounded: it is evaluated on arrival of the second trigger.
Default: 0
RT_THR Input 16 bit BIT VECTOR
New. Threshold on the 4-sample input derivative for the rise-time measure (ADC counts). 0 disables the measure. Typical: just above 4× the per-sample noise.
Default: 0
RT_WINDOW Input 8 bit BIT VECTOR
New. Length (samples) of the rise-time inspection window [trigger−7, trigger−7+RT_WINDOW]. Cover the pulse rise plus the unresolved-pileup region; default 16. Max 255 (ring is 256 deep). Keep RT_WINDOW − 7 ≤ SAMPLE_POS: the rise time is latched RT_WINDOW − 7 samples after the trigger and paired with the event at its sampling point, so a longer window pairs each event with the PREVIOUS event’s rise time (and the first event after a configuration restart carries an undefined one). Minimum 8: a lower value is used as 8.
Default: 16
RT_CUT_EN Input 1 bit BIT
New. 1 = enable the in-IP rise-time cut (gates only ENERGY DV). 0 (default when unconnected) = no cut, RISE_TIME is informative only.
Default: 0
RT_MIN Input 16 bit BIT VECTOR
New. Lower bound of the rise-time acceptance window (accepted if RT_MIN ≤ rise_time ≤ RT_MAX).
Default: 0
RT_MAX Input 16 bit BIT VECTOR
New. Upper bound of the rise-time acceptance window. Defaults to 0xFFFF when unconnected.
Default: 65535
TIMETAG Input 64 bit BIT VECTOR
Free-running 64-bit timestamp; the value latched at the energy sampling point is re-transmitted with the energy word (un-delayed even when the rejector is enabled).
Default: 0
RUN_CFG Input 1 bit BIT
1 = run mode; 0 = configuration/idle. All state (including statistics) is cleared while 0.
Default: 0
TR_RESET Input 1 bit BIT
External reset input, sampled when ENABLE_EXTERNAL_RESET = 1.
Default: 0
EXT_TRIGGER Input 1 bit BIT
External trigger GIN input.
Default: 0
EXT_TRIGGER_SELECTOR Input 4 bit BIT VECTOR
Selector of internal/external trigger mixing: 0=INT, 1=EXT, 2=INT∧EXT, 3=INT∧¬EXT, others reserved. NOTE: with 1 the internal alignment delay TRIG_K + TRIG_M is bypassed, retune SAMPLE_POS.
Default: 0
CLK Input 1 bit BIT
System clock. All inputs/outputs are synchronous to rising edge.
Default: Default Board Clock
RESET Input 1 bit BIT
Asynchronous, active-high global reset of the IP core.
Default: Default Board Reset
DATA_OUT Output ADC_BITS_N bit BIT VECTOR
Aligned input stream monitor.
LEAKAGE_CORRECTED_SIG Output 32 bit BIT VECTOR
ADC sample after leakage subtraction (= the actual energy-trapezoid input), sign-extended to 32 bit.
ENERGY Output 32 bit BIT VECTOR
Sampled energy word $E$ (32-bit signed). Valid when ENERGY DV=1.
ENERGY_STROBE Output 1 bit BIT
One-clock pulse marking a valid ENERGY/TIMESTAMP, FILTERED by the pileup rejector. On the monitor it sits on the flat-top sampling point of the (delayed) trapezoid.
ENERGY_VALID_ALL Output 1 bit BIT
New. One-clock pulse for EVERY sampled event (accepted and pileup-rejected), same alignment as ENERGY DV. The energy/timestamp/rise-time registers update on every event.
RISE_TIME Output 16 bit BIT VECTOR
New. Edge-activity count in the RT window (≈ rise time + 4 for a clean pulse; larger for unresolved pileup). Valid with the strobes, emitted in parallel with ENERGY; updates on every event, including cut/rejected ones.
RT_DISCARDED Output 1 bit BIT
New. One-clock pulse (aligned like the strobes) marking an event suppressed by the rise-time cut.
RT_CUT_CNT Output 32 bit BIT VECTOR
New. Counter of the events discarded by the rise-time cut (cleared by RESET STAT / RUN_CFG=0). Disjoint from the pileup counters.
TRIGGER_OUT Output 1 bit BIT
Validated trigger output (one-clock pulse), aligned with the event on the monitor time base.
TRIGGER_RAW Output 1 bit BIT
New. CFD trigger BEFORE the reset veto, aligned with the event.
TRIGGER_GATED Output 1 bit BIT
New. CFD trigger AFTER the reset veto, aligned with the event.
BASELINE_HOLD Output 1 bit BIT
High while the baseline accumulator is frozen (inhibition window or reset veto).
TIMESTAMP Output 64 bit BIT VECTOR
Timestamp associated with the current ENERGY sample (original, un-delayed tag).
TR_INHIBIT_TRIGGER Output 1 bit BIT
High while the trigger channel is inhibited by a reset event.
PILEUP_WIN_BOTH Output 1 bit BIT
New. High while the kill-both window is open (distance from the last trigger < PILEUP_DIST_BOTH).
PILEUP_WIN_GUARD Output 1 bit BIT
New. High while the kill-second window is open (distance in [PILEUP_DIST_BOTH, PILEUP_DIST_GUARD)).
PILEUP_REJ_BOTH Output 1 bit BIT
New. One-clock marker at the flat-top sampling position of an event discarded by the both rule (the retroactively killed first of a pair included).
PILEUP_REJ_GUARD Output 1 bit BIT
New. One-clock marker at the flat-top sampling position of an event discarded as second-in-guard.
INPUT_CNT Output 32 bit BIT VECTOR
New. Raw CFD trigger counter (pre reset-veto).
INPUT_CNT_GATED Output 32 bit BIT VECTOR
New. Trigger counter gated by the reset veto (does not count inside the veto).
OUTPUT_CNT Output 32 bit BIT VECTOR
New. Emitted energy-word counter (post pileup rejection).
RESET_CNT Output 32 bit BIT VECTOR
New. Pre-amplifier reset counter (one count per reset).
LOST_CNT Output 32 bit BIT VECTOR
New. Triggers suppressed by the reset veto.
ICR Output 32 bit BIT VECTOR
New. INPUT_CNT increments latched every STAT_WINDOW clocks.
ICR_GATED Output 32 bit BIT VECTOR
New. INPUT_CNT_GATED increments latched every STAT_WINDOW clocks.
OCR Output 32 bit BIT VECTOR
New. OUTPUT_CNT increments latched every STAT_WINDOW clocks.
PILEUP_BOTH_CNT Output 32 bit BIT VECTOR
New. Events discarded by the both rule (counted per event, 2 per pair).
PILEUP_GUARD_CNT Output 32 bit BIT VECTOR
New. Events discarded as second-in-guard.
TRIGGER_DELTA_MON Output 32 bit BIT VECTOR
Real-time delta monitor of the trigger CFD.
TRIGGER_TRAP_MON Output 32 bit BIT VECTOR
Trigger trapezoid monitor before threshold comparison.
TRAP_MON Output 32 bit BIT VECTOR
Energy trapezoid monitor.
TRAP_BL_MON Output 32 bit BIT VECTOR
Energy trapezoid minus baseline.
BL_MON Output 32 bit BIT VECTOR
Baseline estimate monitor.

Properties

Property window

Max shaper samples PRE_LEN

This parameters configure the maximum number of samples used by the trapezoidal. It impact of the RAM memory usage in the FPGA

Maximum depth of the energy delay lines (samples). Larger values allow longer peaking times but consume more block-RAM.

Default: 2048

Options: 128 256 512 1024 2048 4096 8192 16384

Max trigger shaper samples TRIGGER_PRE_LEN

This parameters configure the maximum number of samples used by the trigger trapezoidal. It impact of the RAM memory usage in the FPGA

Maximum depth of the trigger delay lines (samples). Must be ≥ TRIG_K + TRIG_M.

Default: 128

Options: 16 32 64 128 256 512

Max baseline samples BASELINE_PRE_LEN

Maximum number of samples of the baseline moving average (RAM usage). Keep it ABOVE PRE_LEN so the baseline preroll outlasts the shaper start-up transient.

Maximum length of the baseline restorer buffer (samples). Must be ≥ 2^BL_LEN. Keep it ABOVE PRE_LEN so the baseline warm-up outlasts the shaper start-up transient.

Default: 2048

Options: 128 256 512 1024 2048 4096 8192 16384

Max trp forecast TR_RESET_DELAY

Number of samples the input can be delayed to let the reset veto anticipate the reset transient (TR PRE GUARD pin upper bound)

Depth of the auxiliary delay line used to hide the reset transient from the trigger path (upper bound of TR_RESET_PRE_GUARD).

Default: 128

Options: 32 64 128 256 512 1024 2048

Input size ADC_BITS_N

Number of bits of the input signal

Width of input bus DATA_IN and internal arithmetic datapath. Changing this parameter resynthesises the core.

Default: 24

Options: 12 14 16 20 24 28 32 64

ADC Bits ADC_BITS_N_EFT

Number of real bits if the ADC connected to the input. (used for saturation and polarity inversion)

Effective ADC resolution used for saturation monitoring and polarity inversion. May differ from ADC_BITS_N.

Default: 20

Options: 12 14 16 18 20 22 24 26 28 30 32

Accumulator size LARGE_ACC_BITS

Accumulator size, depends by the adc number of bit and trapezoidal lenght. Short trapezoidal may have 32 bit acc. At least 64 is reccomanded

Accumulator width in the energy filter. Must be chosen to avoid overflow for the longest peaking time and maximum input signal; at least 64 is recommended.

Default: 64

Options: 32 48 64 80 96 128

Max baseline pre-guard BL_PRE_GUARD_MAX

Upper bound (ring size) of the runtime BL_PRE_GUARD pin: the baseline average can be stopped up to this many samples BEFORE the trigger

Ring size (upper bound) of the runtime BL_PRE_GUARD pin.

Default: 64

Options: 16 32 64 128 256

Enable pileup rejector ENABLE_PILEUP_REJECTOR

Compile the in-IP pileup rejector. Decisions are taken at the energy sampling point, so no output is delayed and the latency is the legacy one. PILEUP DIST BOTH is clamped to SAMPLE_POS at runtime (a second pulse arriving after the first one was sampled cannot corrupt it; use PILEUP DIST GUARD ~ TRAP_K + TRAP_M - SAMPLE_POS for the tail). Default False = rejector logic compiled out.

Compile the in-IP pileup rejector. Decisions are taken at the energy sampling point, so no output is delayed and the latency is the legacy one. Default False = rejector logic compiled out (same behaviour as TRP MCA except the corrected trigger window).

Default: False

Options: False True

Enable rise time ENABLE_RISETIME

Compile the rise-time measure and its optional cut. When True the RT_THR/RT_WIN/RT_CUT_EN/RT_MIN/RT_MAX inputs and the RISE_TIME/RT_DISCARDED/RT_CUT_CNT outputs appear. The measure is inert until RT_THR is set; the cut acts only on ENERGY DV (never on ENERGY DV ALL).

Compile the rise-time measure and its optional cut. When True the RT_THR / RT_WIN / RT_CUT_EN / RT_MIN / RT_MAX inputs and the RISE_TIME / RT_DISCARDED / RT_CUT_CNT outputs appear on the symbol. The measure is inert until RT_THR is set; the cut acts only on ENERGY DV (never on ENERGY DV ALL).

Default: True

Options: False True

Theory of operation

A Jordanov trapezoid is obtained by the difference of two rectangular moving sums:

$$ T[n] = \sum_{i=0}^{k-1}x[n-i] - \sum_{i=k+m}^{2k+m-1}x[n-i] $$

where k is the peaking length and m the gap between the two sums (flat-top duration = m − k). See the TRP MCA guide for the full derivation; this page documents the differences and the new sections.

Trigger filter

Parameters TRIG_K, TRIG_M, THRS. When the delta signal crosses THRS a trigger candidate is armed and validated on the subsequent zero crossing (bipolar CFD detection). The validation window is (TRIG_K + TRIG_M)·2 samples: it always covers the zero crossing, which arrives roughly TRIG_M + rise-time samples after arming. Choose TRIG_K comparable to the input rise time (in samples) for the best time resolution.

The impact of the corrected window, measured on real 2 Mcps SDD data with a ~45 ns rise time: the legacy window lost up to 45 % of the pulses and their un-vetoed trapezoids polluted the baseline. Same data, same parameters, legacy vs TRP NEW:

Effect of the corrected CFD window on the spectrum

The Kα peak more than quadruples in counts, the negative shoulder and the ghost replicas disappear, and the throughput gains ~70 %.

Energy filter and leakage correction

As in TRP MCA (TRAP_K, TRAP_M, TRAP_GAIN, accumulator width LARGE_ACC_BITS), but the input sample is first corrected as

$$ x_\ell[n] = x[n] - \frac{L[n]}{2^{20}},\qquad L[n] = \begin{cases} L[n-1] + \text{LEAKAGE_M} & \text{while no reset}\ \text{LEAKAGE_Q} & \text{immediately after a reset} \end{cases} $$

and $x_\ell[n]$ feeds both the LEAKAGE SIG monitor and the energy trapezoid. With LEAKAGE_M = LEAKAGE_Q = 0 the correction is inert. LEAKAGE_M is expressed in ADC counts per sample times $2^{20}$.

The energy is sampled SAMPLE_POS samples after the trigger: centre it on the flat top, SAMPLE_POS ≈ TRAP_K + (TRAP_M − TRAP_K)/2. The aligned average of TRAP-BL around the sampling strobe, measured on real data, shows the sampling point sitting exactly on the flat-top maximum with the recommended setting:

Average trapezoid profile around the sampling point

Baseline restorer with pre-guard

A moving average of depth $2^{\text{BL LEN}}$ updated only outside the hold windows (each validated trigger re-arms BL_INIB samples of hold; the reset veto holds as well). The BL PRE GUARD pin feeds the average through a delay line while the hold is applied un-delayed: the net effect is that the average stops BL PRE GUARD samples before each trigger, keeping the pulse leading edge out of the baseline. Set BL_INIB ≥ 2·TRAP_K + TRAP_M + BL_PRE_GUARD + margin so the whole trapezoid (now shifted by the pre-guard) stays inside the hold.

The baseline value sampled at each event is the direct spectral error: below, its distribution measured on real 2 Mcps data for baseline lengths 2^4…2^9, legacy (top) versus TRP NEW (bottom — note the ~65× tighter x-scale). The legacy multimodal spikes are the quantized ghosts of un-triggered trapezoids; TRP NEW is Gaussian around zero at every length:

Baseline at the sampling point, legacy vs TRP NEW

Reset veto and guard sizing

After each pre-amplifier reset the energy trapezoid dives strongly negative and needs TRAP_K + TRAP_M samples to recover once the step has transited. The reset veto must keep the baseline held for that whole time, therefore:

$$ \text{TR_RESET_GUARD (after)} ;\ge; \text{TRAP_K} + \text{TRAP_M}

  • \text{TR_RESET_PRE_GUARD} + \text{margin (~100 ns)} $$

A too-short guard produces a negative tail on the left side of the baseline distribution (and a low-energy tail on the peaks), because triggers arriving a few hundred samples after a reset sample a baseline still polluted by the negative recovery. Measured on real data with a 625+125 ns shaping: guard 250 ns (blue) vs 2000 ns (orange):

Baseline histogram vs reset guard length

Statistics block

All counters are 32 bit, cleared by RUN_CFG = 0 or by a high level on RESET STAT:

output meaning
INPUT CNT raw CFD triggers, before the reset veto
INPUT CNT GATED CFD triggers outside the reset veto
OUTPUT CNT energy words emitted (post pileup rejection)
RESET CNT pre-amplifier resets (one count per reset)
LOST CNT triggers suppressed by the reset veto
PU BOTH CNT events discarded by the pileup both rule (2 per pair)
PU GUARD CNT events discarded as second in guard
ICR / ICR GATED / OCR the corresponding counts latched every STAT WINDOW clock cycles

Set STAT WINDOW equal to the clock frequency to read ICR/OCR directly in counts per second (0 disables the rate meters). Note that INPUT CNT counts the internal CFD even when an external trigger is selected through EXT SEL.

Pileup rejector (optional)

Enabled at synthesis time by the ENABLE_PILEUP_REJECTOR property. Let dt be the distance between consecutive accepted triggers (the comparison chain is pairwise recursive: each trigger is compared with the previous one even if that one was already discarded):

  • dt < PU BOTH → both events are discarded;
  • PU BOTH ≤ dt < PU GUARD → only the second event is discarded (it rides on the tail of the first);
  • a threshold set to 0 disables that rule.

How the two rules are evaluated. The second rule (guard) is decided on arrival of the second trigger by comparing the distance from the previous one, whatever the shaping length: PU GUARD is unbounded and costs nothing. The both rule is retroactive for the first event: its verdict is applied when that event is sampled, SAMPLE_POS samples after its trigger, exactly where the legacy strobe fires. It is complete only if PU BOTH ≤ SAMPLE_POS, which is also the physics: a second pulse arriving after the first one has been sampled cannot corrupt that sample (baseline held, trapezoid already read) — discarding the second one is the guard rule’s job. PU BOTH is therefore clamped to SAMPLE_POS at runtime. Recommended: PU BOTH = SAMPLE_POS, PU GUARD ≈ TRAP_K + TRAP_M − SAMPLE_POS (tail of the first trapezoid beyond the sampling point) or more to protect the baseline. Minimum values. Some delay-line taps have a minimum, enforced inside the IP (a lower pin value is used as the minimum): TRIG_K, TRIG_M ≥ 3, TRAP_K, TRAP_M, TR_RESET_PRE_GUARD ≥ 2, SAMPLE_POS ≥ 1, BASELINE_LEN ≥ 2 when not 0, BL_PRE_GUARD ≥ 4, RT_WINDOW ≥ 8. These are the hard limits measured in RTL simulation (shorter taps would read a stale delay-line slot in hardware); short pre-guard values are served from registers, so BL_PRE_GUARD = 4 is exact.

Two pulses closer than the CFD resolution produce a single trigger and cannot be separated by dt: the residual sum peak must be handled by energy cuts.

Alignment. Nothing is delayed: monitors, triggers and windows are on the legacy time base; ENERGY DV, ENERGY, TIMESTAMP, RISE TIME and the reject markers (PU REJ BOTH, PU REJ GUARD) fire at the flat-top sampling point of the trapezoid (SAMPLE_POS after the trigger) like the legacy strobe — rejected events show their marker exactly where their energy would have been sampled, which makes threshold tuning on the scope immediate. PU WIN BOTH / PU WIN GUARD are the live windows opened by the last trigger.

Timing diagrams — real 2 Mcps SDD waveforms as the acquisition software shows them (trap 20/30 samples, SAMPLE_POS 25, PU BOTH 25, PU GUARD 70). An isolated accepted event: the windows open at the trigger, ENERGY DV fires on the flat top:

Isolated accepted event

A pair closer than PU BOTH: both triggers fall inside the red window, two PU REJ BOTH markers, no strobe:

Pair rejected by the BOTH rule

Events in the guard zone: the first is sampled (ENERGY DV), the followers fall in the yellow window and emit PU REJ GUARD:

Second events rejected by the GUARD rule

A pre-amplifier reset: TR INHIBIT rises before the visible ADC cliff (the TR_RESET_PRE_GUARD look-ahead), raw triggers inside the veto have no gated counterpart and no energy is emitted:

Reset veto

Measured effect on the spectrum (real 2 Mcps data, 245 ms, statistics overlay from the IP counters). Rejector off, then PU BOTH = SAMPLE_POS and PU GUARD = 70: the inter-peak continuum drops by about two orders of magnitude and the partial-pileup bump disappears; the residual sum peak (unresolved coincidences) is the target of the rise-time cut below:

Spectrum with the rejector off

Spectrum with BOTH=SAMPLE_POS, GUARD=70

Rise-time measure

In parallel with every energy word the block emits RISE TIME: the number of samples, within a sliding window of RT WIN samples ending just after the trigger ([trigger − 7, trigger − 7 + RT WIN]), where the 4-sample derivative of the (aligned, leakage-corrected) input exceeds RT THR. A clean step gives ≈ input rise time + 4; every additional step landing inside the window adds its own contribution regardless of the separation. Unresolved pileup (two pulses closer than the CFD resolution, which produce a single trigger and a summed energy) therefore shows a distinctly larger value: on real 2 Mcps SDD data a downstream cut at RISE TIME ≤ 9 kept 98.9 % of the Kα peak while removing 73 % of the sum peak. RT THR = 0 disables the measure (output 0). The value is meaningless for events started by the external GIN trigger. The whole feature (ports included) is compiled in by the ENABLE_RISETIME property.

Measured on real 2 Mcps data (RT THR 2000 ADC, RT WIN 16): the rise-time distributions per energy region, the energy-vs-rise-time map (the unresolved-pileup band sits clearly above the photopeaks) and the spectrum with/without the cut:

Rise-time distribution, E-vs-RT map and cut effect

Optional in-IP cut: with RT CUT EN high an event is accepted only if RT MIN ≤ RISE TIME ≤ RT MAX. The cut gates only the filtered ENERGY DV: ENERGY DV ALL and the ENERGY/TIMESTAMP/RISE TIME registers are untouched, so downstream logic can always see every event with its rise time and re-apply its own selection. Each cut event emits a RT DISCARDED pulse (aligned like the strobes) and increments RT CUT CNT. With the pileup rejector enabled the cut is applied AFTER the pileup rules, so RT CUT CNT and the pileup counters are disjoint: ENERGY DV ALL = ENERGY DV + RT CUT + pileup both + pileup guard.

Unfiltered energy valid

ENERGY DV ALL pulses for EVERY sampled event — accepted and pileup-rejected — with the same alignment as ENERGY DV in both modes. The ENERGY / TIMESTAMP / RISE TIME output registers update on every event as well: the pileup rejector only suppresses the filtered ENERGY DV. Downstream logic can thus either take the filtered stream (ENERGY DV) or the full stream (ENERGY DV ALL) and apply its own rejection using RISE TIME and the pileup counters.

Timing

  • Same latencies as TRP MCA with or without the rejector.

FPGA resources

As TRP MCA, plus one small delay line of depth BL_PRE_GUARD_MAX, the rise-time rings (2 × 256 bit) and, when the pileup rejector is compiled in, two rings of depth PRE_LEN (2 bit + 1 bit) parallel to the sampler delay line: about 3 BRAM18 in total at PRE_LEN = 4096.

Typical use-case

A transistor-reset SDD or HPGe detector at high rate (≥ 500 kcps). At 2 Mcps, enabling the rejector with PU BOTH = SAMPLE_POS and PU GUARD ≈ 2·TRAP_K + TRAP_M cleans the inter-peak continuum by about two orders of magnitude at the cost of the corresponding throughput; the statistics outputs give the live ICR/OCR balance needed to compute dead-time-corrected activities.