TM
Block Preview

Introduction

This block performs sign extension on time-multiplexed (TM) data streams. It extends signed two’s complement numbers to wider formats while preserving both the sign and numeric value.

The operation is purely combinational with zero latency. The sign bit (MSB) is replicated to fill all additional MSB positions in the wider output.

This block is used for signed two’s complement numbers only. For unsigned numbers, use Zero Fill instead.

The TM Factor property determines how many parallel samples are processed per clock cycle.

Pin Description

IN Input Variable bit TM
Input binary data (signed two’s complement), always TM. Width: Input Width × TM Factor MSB is the sign bit.
Default: Must be connected
OUT Output Variable bit TM
Sign-extended output (signed two’s complement), always TM. Width: Output Size × TM Factor Output is combinational (zero latency). Sign and value are preserved.

Properties

Property window

Input Width (per phase) InputWidth

Set the input word size in bits per phase

Number of bits per input sample. Range: 2 – 128. Must be ≤ Output Size. MSB is treated as the sign bit.

Default: 16

Range: 2 – 128

TM Factor TMFactor

Set the time multiplexing factor (number of phases)

Time-multiplexing factor (number of parallel phases). Allowed values: 2, 4, 8, 16, 32.

Default: 4

Range: 2 – 32

Output Size (per phase) OutputSize

Set the output word size in bits per phase

Number of bits per output sample. Range: 0 – 128. Must be ≥ Input Width. Additional MSBs are filled with sign bit.

Default: 32

Range: 0 – 128

Functional description

The component implements sign extension in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.

For each TM phase:

  • Input width = Input Width bits
  • Output width = Output Size bits (must be ≥ Input Width)
  • Sign bit = Input MSB (bit Input Width - 1)
  • Extension = Replicate sign bit into all additional MSB positions

Operation

Sign extension preserves the value of two’s complement signed numbers:

$$ y[W_{\text{out}}-1 : W_{\text{in}}] = \text{replicate}(x[W_{\text{in}}-1]) $$

$$ y[W_{\text{in}}-1 : 0] = x[W_{\text{in}}-1 : 0] $$

Examples

Positive number:

  • 8-bit: 01101100 (+108) → 16-bit: 00000000 01101100 (+108)
  • Sign bit (0) replicated to fill upper 8 bits

Negative number:

  • 8-bit: 11010110 (-42) → 16-bit: 11111111 11010110 (-42)
  • Sign bit (1) replicated to fill upper 8 bits

Mathematical background

Sign extension preserves the numeric value in two’s complement representation:

For an N-bit signed number $x$ extended to M bits (M > N): $$ \text{value}(x_{\text{extended}}) = \text{value}(x) $$

Common uses:

  • Signed integer width conversion (8→16, 16→32 bits)
  • Fixed-point signed arithmetic width adaptation
  • ALU operand size normalization
  • Communication protocol signed data conversion

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Sign Extend TM 0

All TM phases are processed in parallel within the same clock cycle.

Typical use cases

  • Signed integer width conversion (8→16, 16→32 bits)
  • Fixed-point signed arithmetic width adaptation
  • DSP pipeline operand size normalization
  • Two’s complement data format conversion
  • Signed audio/video sample processing