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Introduction

This block implements an XOR reduction operation on a multi-bit input vector. It performs a logical XOR across all bits of the input, producing a single-bit output.

The output is 1 (HIGH or True) if an odd number of input bits are 1. The output is 0 (LOW or False) when an even number of input bits are 1 (including zero).

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT} = \mathrm{IN}[0] \oplus \mathrm{IN}[1] \oplus \ldots \oplus \mathrm{IN}[N-1], $$

where $\oplus$ represents the logical XOR operation and $N$ is the input bit width.

Pin Description

IN_0 Input -1 bit BIT VECTOR
OUT Output 1 bit BIT
Single-bit output (1 bit wide). Output is 1 if the input has odd parity (odd number of 1s). Output is 0 if the input has even parity (even number of 1s). Output is combinational (zero latency).
IN Variable bit
Input binary vector. Width: Configurable (typically 1 to 32+ bits). All bits of this vector will be XOR-ed together.
Default: Must be connected

Properties

InputWordSize InputWordSize
Number of bits in the input vector. The XOR reduction operation is applied across all these bits to produce a single-bit output representing the parity.

Functional description

The component implements an XOR reduction operation in VHDL. It takes a multi-bit input vector and reduces it to a single bit by XOR-ing all bits together:

$$ y = \bigoplus_{i=0}^{N-1} x[i], $$

where:

  • $x[i]$ → bit $i$ of the input vector
  • $y$ → single-bit output
  • $\bigoplus$ → XOR reduction operator

This implements parity checking - the output indicates whether the input has odd parity (odd number of 1s):

Input Pattern # of 1s Output
All 0s 0 (even) 0
One 1 1 (odd) 1
Even number of 1s Even 0
Odd number of 1s Odd 1

Example

Given an 8-bit input:

  • 00000000 → Output: 0 (0 ones - even)
  • 00000001 → Output: 1 (1 one - odd)
  • 00000011 → Output: 0 (2 ones - even)
  • 00000111 → Output: 1 (3 ones - odd)
  • 11111111 → Output: 0 (8 ones - even)

Mathematical background

The XOR reduction operation is a unary operator that combines all bits of a vector using the XOR operation. It is fundamental in:

  • Parity generation: Creates odd/even parity bit
  • Error detection: Single-bit error detection in data transmission
  • CRC calculations: Building block for cyclic redundancy checks
  • Checksum generation: Simple data integrity verification

The output is equivalent to the parity bit (odd parity) of the input vector.

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
XOR Reduce 0

The output changes immediately (after propagation delay) when the input changes.

Typical use cases

  • Parity bit generation for error detection
  • Simple checksum calculations
  • Data integrity verification
  • Odd/even detection in bit patterns
  • Building block for CRC and hash functions