Position Sense Detector

Introduction link

The Position Sense Detector (NI_PSA) block calculates the interaction position of a particle (e.g., a neutron) on a position-sensitive detector such as a He3 tube. It measures the energy on both sides of the detector and determines the position from the ratio between one side’s energy and the total energy sum.

Key principle: When a particle interacts with the detector, charge is collected at both ends. The ratio of charge collected at one end to the total charge is proportional to the interaction position along the detector.

$$ \text{Position} = \frac{E_A}{E_A + E_B} $$

where $E_A$ and $E_B$ are the energies measured on side A and side B respectively.

Pin Description link

Properties link

Usage link

Architecture Overview link

The IP integrates two identical signal processing chains for Side A and Side B:

Each processing chain implements:

1. Input stage - Offset subtraction and polarity inversion
2. Signal filter - Quasi-Gaussian shaper (4th order)
3. Trigger circuit - Threshold-based with hysteresis
4. Peak detector - Maximum finder within gate window
5. Output formatter - Packet generation with timestamp

Signal Processing Chain link

The filter chain consists of 5 cascaded blocks:

Each block can be enabled/disabled independently via the FLT_CFG register.

Input Stage link

The input stage performs offset subtraction and optional polarity inversion:

• OFFSET: DC offset value subtracted from the input signal
• POL: When POL=1, the signal is inverted (for negative pulses)

The Gaussian Shaper Filter Explained link

The goal is to implement a quasi-Gaussian pulse shaper that transforms the detector signal into a shape suitable for amplitude measurement.

Why Gaussian Shaping? link

A true Gaussian pulse shape is optimal for:

• Signal-to-noise ratio: Minimizes noise contribution
• Pile-up rejection: Clear separation between pulses
• Amplitude measurement: Peak corresponds to energy

The 4th-Order Approximation link

The analog Gaussian filter uses this normalized transfer function:

$$ H(s) = \frac{4.899}{4.899 + 11.42s + 10.87s^2 + 5.073s^3 + s^4} $$

This filter has 4 complex poles in the s-plane:

• $s_{1,2} = -1.35536 \pm j \cdot 0.32795$
• $s_{3,4} = -1.18108 \pm j \cdot 1.0604$

Digital Implementation link

Using the matched Z-transform method, we map the s-plane poles to z-plane poles:

$$ s_i \rightarrow e^{s_i \cdot T} $$

where $T = \frac{T_s}{2\pi\tau}$, $T_s$ is the sample period, and $\tau$ is the desired shaping time constant.

This results in two cascaded 2nd-order IIR filters (biquad sections):

$$ H_z(z) = \frac{K}{(1 - a_1 z^{-1} + b_1 z^{-2})(1 - a_2 z^{-1} + b_2 z^{-2})} $$

Each 2nd-order section is implemented as:

$$ u[n] = i[n] + a_k \cdot u[n-1] - b_k \cdot u[n-2] $$

Coefficient Calculation link

The filter coefficients depend on two parameters:

• $\tau$ (tau): The Gaussian shaping time constant
• $f_{clk}$: The ADC/system clock frequency

First, calculate the normalized time:

$$ T = \frac{T_s}{2\pi\tau} = \frac{1}{2\pi \cdot \tau \cdot f_{clk}} $$

Then, the four coefficients are:

Understanding the formulas:

• The $a$ coefficients use $2 \cdot e^{-\text{real}} \cdot \cos(\text{imag})$ because they come from conjugate pole pairs
• The $b$ coefficients are simply $e^{-2 \cdot \text{real}}$ (the product of the two conjugate pole magnitudes)

Fixed-Point Scaling link

For FPGA implementation, coefficients are scaled by 16384 ($2^{14}$):

Pole-Zero Compensation link

The pole-zero compensation circuit removes the exponential tail from the preamplifier output.

The Problem link

A charge-sensitive preamplifier produces a signal with exponential decay:

$$ v(t) = V_0 \cdot e^{-t/\tau_l} $$

where $\tau_l$ is the long preamplifier time constant (typically 50-500 $\mu s$).

The Solution link

We want to convert this to a shorter time constant $\tau_s$ (e.g., 8 sample periods). The transfer function is:

$$ H(s) = \frac{s + 1/\tau_l}{s + 1/\tau_s} $$

In digital form:

$$ w[n] = i[n] + \left(1 - \frac{T_s}{\tau_s}\right) \cdot w[n-1] $$

$$ u[n] = i[n] + \left(\frac{T_s}{\tau_l} - \frac{T_s}{\tau_s}\right) \cdot w[n] $$

PZCOEFF Calculation link

The PZCOEFF register is scaled by 32768 ($2^{15}$):

$$ \text{PZCOEFF} = \text{round}\left(\frac{32768}{f_{clk} \cdot \tau_{pz}}\right) $$

where $\tau_{pz}$ is the preamplifier decay time constant.

Python Code for Coefficient Calculation link

  import math

def calculate_psa_coefficients(clock_freq_hz, tau_shaper_s, tau_pz_s):
    """
    Calculate NI_PSA filter coefficients.

    Parameters:
    -----------
    clock_freq_hz : float
        ADC/system clock frequency in Hz (e.g., 125e6 for 125 MHz)
    tau_shaper_s : float
        Gaussian shaper time constant in seconds (e.g., 1e-6 for 1 us)
    tau_pz_s : float
        Preamplifier pole-zero time constant in seconds (e.g., 1e-6 for 1 us)

    Returns:
    --------
    dict : Dictionary with coefficient names and integer values
    """
    # Normalized time parameter
    # T = Ts / (2 * pi * tau) = 1 / (2 * pi * tau * f_clk)
    T = 1.0 / (2 * math.pi * tau_shaper_s * clock_freq_hz)

    # Also written as: TS = (2 * pi) / (tau * clock_freq)
    TS = (2 * math.pi) / (tau_shaper_s * clock_freq_hz)

    # Gaussian filter poles (from 4th-order quasi-Gaussian approximation)
    # Pole pair 1: -1.35536 +/- j*0.32795
    # Pole pair 2: -1.18108 +/- j*1.0604

    # First biquad section coefficients
    # b1 = exp(-2 * real_part * T) = exp(-2.71072 * T)
    # a1 = 2 * exp(-real_part * T) * cos(imag_part * T)
    b1 = math.exp(-2.71072 * TS)
    a1 = 2 * math.exp(-1.35536 * TS) * math.cos(0.327948 * TS)

    # Second biquad section coefficients
    b2 = math.exp(-2.36216 * TS)
    a2 = 2 * math.exp(-1.18108 * TS) * math.cos(1.06037 * TS)

    # Scale to fixed-point (14-bit precision, multiply by 16384)
    coeff11 = int(b1 * 16384 + 0.5)  # b1 scaled
    coeff12 = int(a1 * 16384 + 0.5)  # a1 scaled
    coeff21 = int(b2 * 16384 + 0.5)  # b2 scaled
    coeff22 = int(a2 * 16384 + 0.5)  # a2 scaled

    # Pole-zero coefficient (15-bit precision, multiply by 32768)
    pzcoeff = int(32768 / (clock_freq_hz * tau_pz_s))

    return {
        'COEFF11': coeff11,
        'COEFF12': coeff12,
        'COEFF21': coeff21,
        'COEFF22': coeff22,
        'PZCOEFF': pzcoeff,
        'COEFF11_hex': f'0x{coeff11:04X}',
        'COEFF12_hex': f'0x{coeff12:04X}',
        'COEFF21_hex': f'0x{coeff21:04X}',
        'COEFF22_hex': f'0x{coeff22:04X}',
        'PZCOEFF_hex': f'0x{pzcoeff:04X}'
    }


# Example usage
if __name__ == '__main__':
    # Example: 125 MHz clock, 1 us shaping time, 1 us pole-zero
    coeffs = calculate_psa_coefficients(
        clock_freq_hz=125e6,
        tau_shaper_s=1e-6,
        tau_pz_s=1e-6
    )

    print("NI_PSA Filter Coefficients")
    print("=" * 40)
    print(f"COEFF11 (b1): {coeffs['COEFF11']:5d} = {coeffs['COEFF11_hex']}")
    print(f"COEFF12 (a1): {coeffs['COEFF12']:5d} = {coeffs['COEFF12_hex']}")
    print(f"COEFF21 (b2): {coeffs['COEFF21']:5d} = {coeffs['COEFF21_hex']}")
    print(f"COEFF22 (a2): {coeffs['COEFF22']:5d} = {coeffs['COEFF22_hex']}")
    print(f"PZCOEFF     : {coeffs['PZCOEFF']:5d} = {coeffs['PZCOEFF_hex']}")

    # Verify with known values from documentation
    # For tau=1us, pz=1us, 125MHz: coeff11=0x37d9, coeff12=0x778e, etc.
  

Example Coefficient Values link

Baseline Correction Algorithm link

The baseline correction removes DC offset and compensates for AC coupling effects:

1. Divide samples into chunks of N samples
2. Find the minimum value in each chunk
3. Apply first-order IIR filter to smooth the minimum: $$ w[n] = \frac{1}{k} \cdot \min[n] + \left(1 - \frac{1}{k}\right) \cdot w[n-1] $$
4. Subtract the smoothed baseline from input: $u[n] = i[n] - w[n]$

Default: $k = 32$ (implemented as bit shift)

Trigger System link

Trigger modes (TRG_MODE):

• 0: Sum of both sides (A + B)
• 1: External trigger only
• 2: OR of both sides (A OR B)
• 3: AND of both sides (A AND B)

Trigger features:

• Programmable threshold (TRG_THRES)
• Hysteresis to prevent noise re-triggering (TRG_HIST)
• Holdoff time after trigger (TRG_HOLD)
• Configurable output width (TRG_OUT_W)

Maximum Finder (Peak Detection) link

When triggered, the peak detector:

1. Opens a gate window (GATE_W clock cycles)
2. Monitors the sum signal (A + B)
3. Stores the maximum sum value and corresponding A/B values
4. At gate close, outputs the stored peak values

Pile-up handling:

• If a new trigger occurs during the gate window, the event is marked as pile-up
• The second event is discarded

Output Data Format link

The DATA output is a 128-bit packet:

Flag bits in CH_ID field:

• Bit 0: PILEUP_A
• Bit 1: PILEUP_B
• Bit 2: OVR_A (overflow)
• Bit 3: OVR_B (overflow)

Resources & Timing link

• Latency: Variable (depends on filter configuration)

• Throughput: 1 event per gate window duration

Uses DSP blocks for filter multiplications. Filter configuration and coefficients must be properly calculated for optimal performance.