Xilinx
Block Preview

Introduction

Every CE clock the block outputs $(u_1 + u_2)/2$ where $u_1, u_2$ are two independent uniform samples (the two halves of one 64-bit xoshiro word): a triangular PDF over the full signed range, the classic dither distribution (TPDF). The spectrum is white.

The distribution below is measured on the bit-exact model the hardware is verified against (GHDL golden regression):

Triangular distribution

Pin Description

CE Input 1 bit BIT
Clock enable: one new sample per clock where high. Default: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Restarts the sequence from the seed.
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
Triangular noise sample, signed, OutputBits wide.
DV_OUT Output 1 bit BIT
High on every clock carrying a new sample.

Properties

Property window

Output bits OutputBits

Width of the OUT word (2..32), signed.

Output width (2..32), signed.

Default: 16

Range: 2 – 32

SEED (32 digit hex) SEED

Seed of the embedded white generator (128 bit hex), expanded internally with SplitMix64. Auto-randomized when the component is created, so multiple instances produce independent noise; editable for reproducible runs. RESET restarts the sequence. Triangular amplitude distribution (mean of two uniforms), signed, zero-centered.

128-bit seed of the embedded white generator (auto-randomized at placement, editable).

Default: 5B52559C9AC64259B150A543DDE62757

Usage

The seed is auto-randomized when the block is placed (independent instances) and editable for reproducible runs; RESET restarts the sequence identically. Leaving CE unconnected ties it to ‘1’.