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Introduction

What the block does

PUR_SIMPLE is a pile-up rejector: it examines the time distance between consecutive trigger pulses (TRIGGER_IN) and discards events that arrive too close to a previously accepted one.
Two programmable windows are implemented:

  1. Dead-Time (DLENGTH) – a strict inhibit period in which every incoming pulse is always rejected (hard dead-time).
  2. Guard-Time (LENGTH) – a softer extension that still keeps the PUR busy (event rejected) but allows the next clean event to be accepted if no further pile-up occurs.

The block can optionally work in parallelisable mode (PARAL = ’1’), which immediately resets the windows every time a new pile-up candidate is detected, emulating a “sliding” dead-time behaviour.

Pin Description

ENERGY_IN Input BITSIZE bit BIT VECTOR
Input energy word. Width is set by BITSIZE (default = 16).
Sampled on the rising edge of CLK only when TRIGGER_IN = '1'.
Default: Must be connected
TRIGGER_IN Input 1 bit BIT
Digital valid-pulse associated with ENERGY_IN.
A rising edge starts the inter-arrival time measurement.
Must satisfy a single-clock high-pulse protocol.
Default: Must be connected
LENGTH Input 32 bit BIT VECTOR
Guard-time T_G in clock cycles (32-bit unsigned).
When inib_counter3 (dead-time) expires, the FSM keeps INIB high for LENGTH additional clocks before forwarding the stored event.
Default: 0
DLENGTH Input 32 bit BIT VECTOR
Dead-time T_D in clock cycles (32-bit unsigned).
Defines the strict period in which all incoming triggers are rejected (DINIB = 1).
Default: 0
PARAL Input 1 bit BIT
Parallelisable mode enable.
• 0 – Non-parallel: windows are fixed after the first pulse.
• 1 – Parallel: windows are re-loaded every time a new pulse arrives during inhibition, emulating a sliding dead-time.
Default: 0
CLK Input 1 bit BIT
System clock. All synchronous operations occur on its rising edge.
Must be common to every TM block within the design.
Default: Default Board Clock
RESET Input 1 bit BIT
Asynchronous, active-high reset.
Clears the FSM to State 0 and forces all outputs low.
Default: Default Board Reset
ENERGY_OUT Output 16 bit BIT VECTOR
Accepted energy sample, registered one clock after the end of INIB.
Valid only when DV_OUT = '1'.
DV_OUT Output 1 bit BIT
Data-valid flag for ENERGY_OUT.
Asserted for one clock cycle for every accepted event.
INIB Output 1 bit BIT
Global inhibit flag (high during both dead-time and guard-time).
Can be used by downstream logic to disable integrators or shapers.
DINIB Output 1 bit BIT
Dead-time inhibit flag (subset of INIB).
High only during the strict dead-time DLENGTH.
INIB_GUARD Output 1 bit BIT
Internal guard indicator used by the FSM to block acceptance while DINIB has already elapsed but residual pulses are still pending.
REJ Output 1 bit BIT
Rejection flag for pulses arriving after DLENGTH but before the current guard-time has finished.
DREJ Output 1 bit BIT
Double-rejection flag for pulses arriving inside the current DLENGTH.
Useful for estimating pile-up statistics.

Properties

Property window

Event Size BITSIZE

This parameters sets the number of bits for the Input and Output Event size

Defines the bit-width of both ENERGY_IN and ENERGY_OUT.
Accepted range: 1 – 32 (synthesis must fit the target device).
Higher BITSIZE increases resource usage on the DSP and routing network but allows larger ADC dynamic range.

Default: 16

Functional description

Let

$t_i$ be the arrival time of the i-th trigger pulse, $\Delta t_i = t_i - t_{i-1}$ the inter-arrival time, $T_D$ the dead-time (DLENGTH), $T_G$ the guard-time (LENGTH).

The PUR finite-state machine (FSM) behaves as follows:

  • State 0 – Idle
    Waits for the rising edge of TRIGGER_IN (ddvin). When detected, it
    sets
    $$ \text{inibCounter2} \leftarrow T_G + T_D,\qquad \text{inibCounter3} \leftarrow T_D $$
    and raises INIB and DINIB.

  • State 1 – Dead-Time
    DINIB stays high for exactly DLENGTH clocks.
    Any pulse within this window sets DREJ = 1.
    If PARAL = ’1’, the counters are re-loaded so that the dead-time slides with every new pile-up; otherwise the counters just decrement.

  • State 2 – Guard-Time
    DINIB is cleared, INIB may remain high until the residual part
    of inib_counter2 expires.
    The first clean pulse that appears after guard-time is accepted:
    its energy word is forwarded to ENERGY_OUT, DV_OUT is asserted for one clock, and the FSM returns to State 0.
    Any pulse arriving while INIB is still high but outside DINIB raises REJ = 1.

Mathematical model

An event i is accepted if

$$\Delta t_i \ge T_D + T_G$$

in non-parallel mode, or

$$\Delta t_i \ge T_D \quad\text{and no other trigger inside }[t_{i-1},;t_i)$$

in parallel mode (sliding dead-time).

Timing

  • Latency:
    The data word captured at the end of guard-time is delivered to ENERGY_OUT with DV_OUT = 1 after 1 clock cycle thanks to the PIPELINE II=1 directive.
  • Throughput:
    One accepted event per clock when the windows are inactive.

Typical use case

PUR_SIMPLE is commonly placed after a leading edge discriminator in gamma-ray or particle spectroscopy chains to guarantee the purity of the energy spectrum by rejecting pile-up events that would bias amplitude estimation.

Pile-up Rejector