Block Preview

Introduction

This block implements an OR reduction operation on a multi-bit input vector. It performs a logical OR across all bits of the input, producing a single-bit output.

The output is 1 (HIGH or True) if at least one input bit is 1. The output is 0 (LOW or False) only when the input vector contains all 0s.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT} = \mathrm{IN}[0] \lor \mathrm{IN}[1] \lor \ldots \lor \mathrm{IN}[N-1], $$

where $\lor$ represents the logical OR operation and $N$ is the input bit width.

Pin Description

IN_0 Input -1 bit BIT VECTOR
OUT Output 1 bit BIT
Single-bit output (1 bit wide). Output is 1 if at least one input bit is 1. Output is 0 if and only if all input bits are 0. Output is combinational (zero latency).
IN Variable bit
Input binary vector. Width: Configurable (typically 1 to 32+ bits). All bits of this vector will be OR-ed together.
Default: Must be connected

Properties

InputWordSize InputWordSize
Number of bits in the input vector. The OR reduction operation is applied across all these bits to produce a single-bit output.

Functional description

The component implements an OR reduction operation in VHDL. It takes a multi-bit input vector and reduces it to a single bit by OR-ing all bits together:

$$ y = \bigvee_{i=0}^{N-1} x[i], $$

where:

  • $x[i]$ → bit $i$ of the input vector
  • $y$ → single-bit output
  • $\bigvee$ → OR reduction operator

This is equivalent to checking if any bit is 1 in the input vector:

Input Pattern Output
All 0s 0
Any 1 1

Example

Given an 8-bit input:

  • 00000000 → Output: 0 (all bits are 0)
  • 00000001 → Output: 1 (at least one bit is 1)
  • 10101010 → Output: 1 (multiple bits are 1)

Mathematical background

The OR reduction operation is a unary operator that combines all bits of a vector using the OR operation. It is commonly used in VHDL/Verilog for:

  • Checking if any bit in a vector is set (non-zero detection)
  • Validating that at least one condition is true
  • Implementing “any true” conditions
  • Zero detection (inverse of OR reduce)

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
OR Reduce 0

The output changes immediately (after propagation delay) when the input changes.

Typical use cases

  • Non-zero detection in data validation
  • Checking if any error flag is set
  • Implementing “any condition met” logic
  • Bit-width reduction in status monitoring
  • Activity detection across multiple signals