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Introduction

Pink noise has equal power per octave ($1/f$ PSD, -3 dB/oct) – the spectrum of flicker noise and the standard wideband test stimulus. The Voss-McCartney construction sums Octaves random registers where register $j$ is refreshed with new white every $2^j$ samples: each register contributes one octave band, and the sum approximates $1/f$ within ~0.5 dB over the covered octaves.

Pink noise PSD

Measured on the bit-exact model the hardware is verified against; the dashed line is the ideal -3 dB/octave slope. Below $f_s/2^{Octaves}$ the spectrum flattens to white – add octaves to push the corner down (16 octaves at 100 MHz reaches ~1.5 kHz).

Pin Description

CE Input 1 bit BIT
Clock enable: one new sample per clock where high. Default: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Clears the octave registers and restarts from the seed.
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
Pink noise sample, signed, OutputBits wide, saturated.
DV_OUT Output 1 bit BIT
High on every clock carrying a new sample.

Properties

Property window

Output bits OutputBits

Width of the OUT word (2..32), signed.

Output width (2..32), signed, saturated.

Default: 16

Range: 2 – 32

Octaves Octaves

Number of Voss-McCartney octave registers: the -3 dB/oct slope holds from fs/2 down to fs/2^Octaves (flat/white below).

Voss-McCartney octave registers (4..24): -3 dB/oct holds from fs/2 down to fs/2^Octaves.

Default: 16

Range: 4 – 24

SEED (32 digit hex) SEED

Seed of the embedded white generator (128 bit hex), expanded internally with SplitMix64. Auto-randomized when the component is created, so multiple instances produce independent noise; editable for reproducible runs. RESET restarts the sequence. Pink 1/f noise, -3 dB/octave (Voss-McCartney).

128-bit seed of the embedded white generator (auto-randomized at placement, editable).

Default: 5CE47D2D3D30409AA18E66A84EC535B5

Usage

Output = sum of the Octaves+1 terms, normalized (shift) and saturated to OutputBits. One sample per CE clock, one clock latency. CE defaults to ‘1’.