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Introduction

The TRP MCA block implements a pair of trapezoidal filters:

  • a fast trigger filter, generating a low-latency TRIGGER_OUT;
  • a slow energy filter delivering the shaped amplitude (DATA_OUT) and a time-aligned energy sample (ENERGY).

Unlike classical spectroscopy chains, the pre-amplifier used here is periodically reset, producing a staircase at the ADC input.
Consequently: • the exponential deconvolution stage normally required for RC pre-amps is not present;
• a leakage-current estimator / subtractor keeps the staircase flat between resets;
• an internal reset detector inhibits filtering during the large perturbation introduced by each reset.

The overall data path is fully streaming (II = 1) and can be used in either time-multiplexed or parallel designs. A single clock domain must be provided

Pin Description

DATA_IN Input ADC_BITS_N bit BIT VECTOR
Unsigned ADC sample bus (LSB = 1 count). Width configured through property ADC_BITS_N (default 24 bit).
Default: Must be connected
POLARITY Input 1 bit BIT
1 = pulses are positive; 0 = pulses are negative. Selects internal inversion path.
Default: 0
OFFSET Input ADC_BITS_N+1 bit BIT VECTOR
Two’s-complement digital offset added after polarity inversion. Used to shift the staircase towards mid-code.
Default: 0
THRS Input ADC_BITS_N bit BIT VECTOR
Signed trigger threshold expressed in delta units (see Eq. Δ[n]).
Default: 0
TRIG_K Input 16 bit BIT VECTOR
Peaking length k (samples) for the trigger trapezoid.
Default: 0
TRIG_M Input 16 bit BIT VECTOR
Gap length m (samples) for the trigger trapezoid.
Default: 0
TRAP_K Input 16 bit BIT VECTOR
Peaking length k (samples) for the energy trapezoid.
Default: 0
TRAP_M Input 16 bit BIT VECTOR
Gap length m (samples) for the energy trapezoid.
Default: 0
TRAP_GAIN Input 24 bit BIT VECTOR
Post-filter gain $G$ coded as Q8.16 (default unity = 0x00010000).
Default: 0
BL_LEN Input 4 bit BIT VECTOR
Baseline average depth exponent. Actual length = 2^BL_LEN samples.
Default: 0
BL_INIB Input 16 bit BIT VECTOR
Number of samples to inhibit baseline update after every trigger (BL_HOLD).
Default: 0
SAMPLE_POS Input 16 bit BIT VECTOR
Delay between trigger validation and energy sampling (samples).
Default: 0
LEAKAGE_M Input ADC_BITS_N bit BIT VECTOR
Increment added to leakage accumulator each clock (signed Q4.20).
Default: 0
LEAKAGE_Q Input ADC_BITS_N bit BIT VECTOR
Initial leakage accumulator value loaded at every reset (signed Q4.20).
Default: 0
ENABLE_EXTERNAL_RESET Input 1 bit BIT
1 = use pin TR_RESET; 0 = use automatic reset detector.
Default: 0
HIGH_RATE_MODE Input 1 bit BIT
High rate mode, static configuration input (labelled HI-RATE on the block, defaults to ‘0’ when left unconnected). It changes ONE thing: the trigger dead time after a preamplifier reset. With HIGH_RATE_MODE low the trigger path is inhibited for a whole baseline window plus 20 samples after each detected reset; with it high that preroll is zero, so triggering resumes as soon as the reset guard window itself expires. Fewer events are lost at high rate, at the cost of accepting triggers while the baseline estimate is still recovering. It does not change the trapezoid arithmetic, the baseline estimator or the gains.
TR_RESET_THRESHOLD Input ADC_BITS_N bit BIT VECTOR
ADC level below which a pre-amplifier reset is declared.
Default: 0
TR_RESET_GUARD Input 16 bit BIT VECTOR
Duration (samples) of trigger inhibition after a reset.
Default: 0
TR_RESET_PRE_GUARD Input 16 bit BIT VECTOR
Input delay applied to ADC before reset detection, preventing the reset transient entering the trigger path.
Default: 0
TIMETAG Input 64 bit BIT VECTOR
Free-running 64-bit timestamp sampled at the leading edge of TRIGGER_OUT and re-transmitted with energy word.
Default: 0
RUN_CFG Input 1 bit BIT
1 = run mode; 0 = configuration/idle. All accumulators frozen while 0.
Default: 0
TR_RESET Input 1 bit BIT
External reset input, sampled when ENABLE_EXTERNAL_RESET = 1.
Default: 0
EXT_TRIGGER Input 1 bit BIT
External trigger GIN input.
Default: 0
EXT_TRIGGER_SELECTOR Input 4 bit BIT VECTOR
Selector of internal/external trigger mixing: 0=INT, 1=EXT, 2=INT∧EXT, 3=INT∧¬EXT, others reserved.
Default: 0
CLK Input 1 bit BIT
System clock. All inputs/outputs are synchronous to rising edge.
Default: Default Board Clock
RESET Input 1 bit BIT
Asynchronous, active-high global reset of the IP core.
Default: Default Board Reset
DATA_OUT Output ADC_BITS_N bit BIT VECTOR
Continuous trapezoidal output stream (TRAP_MON).
LEAKAGE_CORRECTED_SIG Output 32 bit BIT VECTOR
Instantaneous ADC sample after leakage subtraction, sign-extended to 32 bit.
ENERGY Output 32 bit BIT VECTOR
Sampled energy word $E$ (32-bit signed). Valid when ENERGY_STROBE=1.
ENERGY_STROBE Output 1 bit BIT
One-clock pulse marking a valid ENERGY and TIMESTAMP.
TRIGGER_OUT Output 1 bit BIT
Validated trigger output (one-clock pulse).
BASELINE_HOLD Output 1 bit BIT
High while baseline accumulator is frozen (during inhibition window).
TIMESTAMP Output 64 bit BIT VECTOR
Timestamp associated with the current ENERGY sample.
TR_INHIBIT_TRIGGER Output 1 bit BIT
Goes high while trigger channel is inhibited by a reset event.
TRIGGER_DELTA_MON Output 32 bit BIT VECTOR
Real-time delta (Δ[n]) monitor for debugging/diagnostics.
TRIGGER_TRAP_MON Output 32 bit BIT VECTOR
Trigger trapezoid monitor ( ΣΔ ) before threshold comparison.
TRAP_MON Output 32 bit BIT VECTOR
Energy trapezoid monitor before gain scaling.
TRAP_BL_MON Output 32 bit BIT VECTOR
Energy trapezoid minus baseline.
BL_MON Output 32 bit BIT VECTOR
Baseline estimate monitor.

Properties

Property window

Max shaper samples PRE_LEN

This parameters configure the maximum number of samples used by the trapezoidal. It impact of the RAM memory usage in the FPGA

Maximum depth of the energy delay lines (samples). Larger values allow longer peaking times but consume more block-RAM.

Default: 2048

Options: 128 256 512 1024 2048 4096 8192 16384

Max trigger shaper samples TRIGGER_PRE_LEN

This parameters configure the maximum number of samples used by the trigger trapezoidal. It impact of the RAM memory usage in the FPGA

Maximum depth of the trigger delay lines (samples). Must be ≥ TRIG_K + TRIG_M.

Default: 128

Options: 16 32 64 128 256 512

Max baseline samples BASELINE_PRE_LEN
Maximum length of baseline restorer buffer (samples). Must be ≥ 2^BL_LEN.

Default: 2048

Options: 128 256 512 1024 2048 4096 8192 16384

Max trp forecast TR_RESET_DELAY
Depth of auxiliary delay line used to hide the reset transient from the trigger path (samples).

Default: 128

Options: 32 64 128 256 512 1024 2048

Input size ADC_BITS_N
Width of input bus DATA_IN and internal arithmetic datapath. Changing this parameter resynthesises the core.

Default: 24

Options: 12 14 16 20 24 28 32 64

ADC Bits ADC_BITS_N_EFT
Effective ADC resolution used for saturation monitoring. May differ from ADC_BITS_N in over-range conditions.

Default: 20

Options: 12 14 16 18 20 22 24 26 28 30 32

Accumulator size LARGE_ACC_BITS
Accumulator width in the energy filter. Must be chosen to avoid overflow for the longest peaking time and maximum input signal.

Default: 64

Options: 32 48 64 80 96 128

Theory of operation

A Jordanov trapezoid is obtained by the difference of two rectangular moving sums:

$$ T[n] = \sum_{i=0}^{k-1}x[n-i] - \sum_{i=k+m}^{2k+m-1}x[n-i] $$

where
k = flat-top/peaking length,
m = gap between the two sums.

The digital implementation used here is split in three sections:

Trigger filter

Implemented with parameters TRIG_K, TRIG_M, THRS.
The instantaneous delta
$$ \Delta[n] = \sum_{i=0}^{k-1}x[n-i] - \sum_{i=k+m}^{2k+m-1}x[n-i] $$
is compared with THRS. Once the threshold is crossed, a trigger candidate is opened for (2·k) samples and validated if the delta subsequently changes sign (bipolar detection).
Guard windows (TR_INHIBIT_TRIGGER) protect the chain after each reset.

1.2 Energy filter

Using TRAP_K, TRAP_M, TRAP_GAIN the shaped signal is
$$ S[n] = \frac{G}{2^{16}}, \Bigl[\sum_{i=0}^{k-1}x[n-i]-\sum_{i=k+m}^{2k+m-1}x[n-i]\Bigr] $$

An accumulator of LARGE_ACC_BITS guarantees distortion-free long integrations.

Leakage current cancellation

The ADC sample $x[n]$ is corrected as
$$ x_\ell[n] = x[n] - \frac{L[n]}{2^{20}} $$

with

$$ L[n] = \begin{cases} L[n-1] + \text{LEAKAGEM} & \text{while no reset} \ \text{LEAKAGEQ} & \text{immediately after reset.} \end{cases} $$

Leakage current compensation

Baseline restorer

A moving average of depth $2^{\text{BLLEN}}$ tracks the residual baseline while ignoring a configurable inhibition window BL_INIB after each validated trigger.

Energy sampler

After a programmable delay SAMPLE_POS, the value
$E = S[n]-\text{Baseline}$
is captured and flagged on ENERGY_STROBE. The 64-bit TIMESTAMP present at the trigger leading edge is re-broadcast to keep event/energy correlation.

Reset detection

If ENABLE_EXTERNAL_RESET = 0 the ADC stream is monitored; whenever
$$ x[n] < \text{TrResetThreshold} $$
a reset is declared and the processing chain is inhibited for TR_RESET_GUARD samples. Pre-guard delay TR_RESET_PRE_GUARD ensures that the large glitch never pollutes the trigger pipeline.

Trapezoidal Shaper

Timing

For continuous streaming:

  • Trigger latency
    $$L_{trig} \approx 2k+m+6\text{ clk}$$
    (k and m refer to TRIG_K, TRIG_M).

  • Shaper output latency
    $$L_{shaper} \approx 2k+m+6\text{ clk}$$
    (k and m refer to TRAP_K, TRAP_M).

  • Energy latency
    $$L_E = L_{shaper} + \text{SamplePos}$$

All internal pipelines are one-sample-per-clock (II = 1).

FPGA resources

Memory usage grows linearly with the maximum depths selected in the properties panel
(PRE_LEN, TRIGGER_PRE_LEN, BASELINE_PRE_LEN, TR_RESET_DELAY).
The provided default (2048 samples) fits comfortably in one BRAM18 per delay line on a typical Series-7 FPGA.

Typical use-case

A transistor-reset HPGe detector is digitised by the ADC; the TRP MCA produces a dead-time-free energy spectrum while suppressing leakage drift and reset artefacts.

Trapezoidal Output