Xilinx
TM
Block Preview

Introduction

Identical to FFT TM Realtime (same polyphase architecture, same output mapping: at DV cycle $k$ lane $q$ carries bin $k + qN/R$, same FRAME_START/FRAME_END markers) with a window $w[n]$ applied to the samples before the transform. The window is stored in polyphase form (one Q16 ROM per TM lane, $ROM_r[m] = w[mR+r]$) and multiplied in a 2-stage pipeline, index-locked to the engine frame counter.

Double-clicking opens the shared FFT Windowed designer (window family + parameter, test tones with per-tone phase, spectrum preview, CSV export). The algorithm/overlap controls are hidden: with a TM input the output port already carries R bins per clock continuously, so frames are back to back (100% coverage, gapless) and no overlap option exists - overlapped frames would need 2R output lanes.

Pin Description

DATA_IN Input 16 bit TM
TM input bus, R x InputBits (lane r = sample n, n mod R = r).
Default: Must be connected
CLK Input 1 bit BIT
TM-domain clock.
Default: Default Board Clock
OUT_RE Output 27 bit TM
TM spectrum, real parts: lane q = bin k + qN/R at DV cycle k.
OUT_IM Output 27 bit TM
TM spectrum, imaginary parts (same mapping).
DV Output 1 bit BIT
High continuously in steady state (gapless).
FRAME_START Output 1 bit BIT
Pulse on the DV cycle carrying bin 0 of each frame.
FRAME_END Output 1 bit BIT
Pulse on the last DV cycle of each frame.

Properties

Property window

FFT Length FFTLength

Transform length N (power of 2)

Transform length N (64..16384, power of 2).

Default: 1024

Options: 64 128 256 512 1024 2048 4096 8192 16384

TM Factor (SSR) TMFactor

Time Multiplexing factor (samples per clock). 2 or 4 (multiplier-free recombination).

TM factor R: 2 or 4.

Default: 4

Options: 2 4

Input Data Bits InputBits

Bit width of each input sample (8-24 bits)

Input sample width (8..24, signed).

Default: 16

Options: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Scaling Mode ScalingMode

No Scaling: full bit growth (InputBits + log2(N) + 1). Grow to Max: saturated to 27 bits. Scale: output divided by N, InputBits wide (saturated).

No Scaling (full growth), Grow to Max (27 bit) or Scale (/N, InputBits wide).

Default: No Scaling

Options: No Scaling Grow to Max Scale

Window Window

Window family (set by the designer, double-click the block)

Window family - set from the designer (double click).

Default: Hann

Config (JSON, use designer) WFProject

Designer state incl. window coefficients (Q16)

Properties and scaling

FFTLength 64..16384, TM factor 2/4, InputBits 8..24 and the same ScalingMode as FFT TM Realtime (No Scaling / Grow to Max / Scale).

Verified in simulation (N=1024, R=4, Hann): 37 back-to-back frames, DV gapless, spectra match the numpy windowed FFT within 7e-5 with the window exactly aligned to the frame boundaries.

Runtime window : FFT Windowed TM Prog

Same engine with the window in RAM: write coefficient $w[n]$ (Q16, 65535 = 1.0) at address $n$ with one COEF_WE pulse; rectangular until loaded. Generate the file with the designer CSV export (same format as the non-TM programmable block). Load while idle.