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Introduction

The QDC block calculates the total charge of a detector pulse by summing consecutive N samples of the input stream DATA_IN. The integration window is started by the rising edge of TRIGGER and can optionally include a programmable number of pre-samples (PRE_TRIGGER).

Key features

  • 16-bit to 32-bit input / 16-bit to 32-bit output.
  • Programmable integration length, pre-trigger depth, pile-up inhibition, digital gain and offset.
  • Real-time pile-up rejection with optional enable.
  • One-cycle throughput, deterministic latency.

Pin Description

DATA_IN Input Wordsize bit BIT VECTOR
Unsigned input sample stream to be integrated.
Width = Wordsize bits. Values are not inverted internally (negative pulses must be pre-processed).
TRIGGER Input 1 bit BIT
Rising edge starts a new integration window.
If asserted while BUSY is high and pile-up rejection is enabled, the event is discarded and PILEUP_WIN is raised.
BASELINE Input Wordsize bit BIT VECTOR
DC offset of the signal, subtracted from every sample before accumulation: $x[n] = \texttt{DATA\_IN} - \texttt{BASELINE}$.
Default: 0
INT_SAMPLES Input 16 bit BIT VECTOR
Number of samples to be integrated ($N_\text{int}$).
1 … 65 535. Programmable through the control bus; stable during run time.
Default: 0
PRE_TRIGGER Input 16 bit BIT VECTOR
Depth of the circular buffer holding samples that precede the trigger ($N_\text{pre}$). Allows the integration window to start before the trigger edge.
Default: 0
GAIN Input 16 bit BIT VECTOR
16-bit fractional gain coefficient.
$$E_\text{raw} = Q \cdot \frac{\texttt{GAIN}}{2^{16}}$$
Setting GAIN = 0xFFFF leaves $Q$ unchanged.
Default: 0
Q_OFFSET Input 16 bit BIT VECTOR
Signed 16-bit offset added after gain multiplication. Useful to remove residual pedestal or to align multiple channels.
Default: 0
PILEUP_EXTRA Input 16 bit BIT VECTOR
Length of pile-up inhibition window (in samples). The counter is reloaded every time a new trigger is detected while inhibiting.
Default: 0
PILEUP_EN Input 1 bit BIT
Enables pile-up rejection when high. If low, all triggers are accepted and the user must handle overlaps externally.
Default: 0
CE Input 1 bit BIT
Clock enable. When low the core keeps its state and no processing is performed.
Default: 1
CLK Input 1 bit BIT
System clock. All synchronous inputs are sampled on the rising edge.
Default: Default Board Clock
RESET Input 1 bit BIT
Asynchronous, active-high reset that clears the FSM, accumulators and status flags.
Default: Default Board Reset
MONITOR Output 16 bit BIT VECTOR
Real-time copy of the delayed sample that is currently entering the integrator (DATA_IN shifted by PRE_TRIGGER).
CHARGE Output Wordsize bit BIT VECTOR
OutputWordSize-bit saturated energy word $E$. Valid only when DV is high.
DV Output 1 bit BIT
Data valid strobe. One-cycle pulse coincident with CHARGE word.
INTEGRATOR Output 32 bit BIT VECTOR
Gate signal that remains high during the accumulation phase (BUSY while the FSM is in state D_INTEGRATE).
INT_MON Output 1 bit BIT
32-bit internal accumulator (Q) for debugging/monitoring purposes.
PILEUP_WIN Output 1 bit BIT
Asserted while the pile-up inhibition window is active or when a pile-up condition has been detected.
LOST Output 1 bit BIT
Pulse indicating that a trigger occurred while the core was busy and pile-up rejection was disabled; the corresponding event is lost.
BUSY Output 1 bit BIT
High from the first accepted trigger until DV or end of pile-up window. Indicates that the core cannot accept a new valid event.

Properties

Property window

Input n bit Wordsize

Set the analog channel word size in bits

Width (in bits) of DATA_IN. Affects accumulator width and resource utilisation. Must be the same for input and baseline.

Default: 16

Options: 16 24 32

Pre-trigger samples PreTriggerWindows

Set the number of max number of pre-trigger samples

Maximum size of the pre-trigger circular buffer (PRE_LEN) compiled into the core. Limits the range of PRE_TRIGGER.

Default: 128

Range: 1 – 4095

QDC output n bit OutputWordSize

Set the output word size in bits

Width (in bits) of CHARGE. Hard-coded to 16 in the current release; changing it requires regenerating the RTL.

Default: 16

Options: 16 24 32

Operating principle

Let the digitised input samples be denoted by
$x[n] = \texttt{DATA\_IN}[n] - \texttt{BASELINE}$.

During an integration window of length $N_\text{int}$ (set by INT_SAMPLES) the accumulated charge is

$$ Q = \sum_{k=0}^{N_\text{int}-1} x[n-k-N_\text{pre}], $$

where $N_\text{pre}$ (PRE_TRIGGER) is the number of samples that precede the trigger and are therefore read from the circular pre-buffer.

The final 16-bit energy word is

$$ E = \operatorname{sat}_{16} \left( \frac{Q \cdot \texttt{GAIN}}{2^{16}} + \texttt{Q\_OFFSET} \right), $$

where sat₁₆ denotes saturation to the unsigned 16-bit range $[0,2^{16}-1]$.

Pile-up rejection

If PILEUP_EN is high, every subsequent trigger that arrives within the inhibition window PILEUP_EXTRA aborts the current integration, sets PILEUP_WIN, and restarts the rejection counter. When the counter expires the state machine returns to idle.

pileup-rejector2.png

Timing

The core is fully pipelined with an initiation interval of 1 clock cycle.
Latency from the first sample that belongs to the integration window to the assertion of DV is

$$ L = N_\text{int} + 2 ;\text{cycles}. $$

  • 1 cycle: CHECKVALUE stage
  • 1 cycle: HIST (output-formatting) stage

Additional fixed delay introduced by the pre-buffer is PRE_TRIGGER cycles, but this does not affect system latency because those samples are stored in parallel with the incoming stream.

Images

charge_integrator.png