Xilinx
TM
HLS
Block Preview

Introduction

The block computes, in fixed-point arithmetic, $$ \mathrm{MAG} = \sqrt{X^2+Y^2}, \quad \mathrm{PHASE} = \operatorname{atan2}(Y, X) $$ This is the time-multiplexed variant: the X port carries TM samples packed side by side in one wide vector, and the same operation is applied to every slot in the same clock cycle. The scalar variant fixedp_r2p is identical apart from the packing.

Operand Y can either be time-multiplexed as well (slot by slot operation) or a single scalar broadcast to every slot, selected by the B_IsTM property.

Every operand and every result carries its own Q format: the number of integer bits, the number of fractional bits and the sign are chosen independently. The binary point is tracked through the whole datapath, so operands with different scaling are aligned automatically – no manual shifting is required, which is the main practical difference with respect to the integer-only arithmetic blocks.

Input domain. At the origin the magnitude is zero and the phase is reported as zero.

Pin Description

X Input Variable bit TM
Time-multiplexed input operand. Width: (X Integer Bits + X Fractional Bits) x TM Factor.
Default: Must be connected
Y Input Variable bit TM
Second operand. When B_IsTM = YES the width is (Y Integer Bits + Y Fractional Bits) x TM Factor and the operation is applied slot by slot; when NO the port is a single sample broadcast to every slot.
Default: Must be connected
IN_DV Input 1 bit BIT
Input data valid, active high. Tie to ‘1’ for free running operation.
MAG Output 17 bit TM
Result, format Q(MAG Integer Bits . MAG Fractional Bits). Width: (MAG Integer Bits + MAG Fractional Bits) x TM Factor, packed like the inputs.
PHASE Output 17 bit TM
Result, format Q(PHASE Integer Bits . PHASE Fractional Bits). Width: (PHASE Integer Bits + PHASE Fractional Bits) x TM Factor, packed like the inputs.
OUT_DV Output 1 bit BIT
Output data valid, asserted when the result is available.
NAN Output 1 bit BIT
Result undefined, asserted together with OUT_DV for the sample it qualifies: both inputs are zero: the phase of the zero vector is undefined. OUT still carries the best defined value the block can produce, so this pin is the only way to know it is not the answer to the question asked. NAN suppresses OL and UL. One bit for the whole TM word: the flag is the OR across the slots.
OL Output 1 bit BIT
Overflow: the true result left the OUT format and was saturated - wrapped instead, when Enable Saturation is NO. Asserted together with OUT_DV, mutually exclusive with UL, and suppressed by NAN. One bit for the whole TM word: the flag is the OR across the slots.
UL Output 1 bit BIT
Underflow: the true result was NOT zero but requantised to zero in the OUT format, i.e. the whole value was lost. Asserted together with OUT_DV, mutually exclusive with OL, and suppressed by NAN. One bit for the whole TM word: the flag is the OR across the slots.
CLK
Processing clock, connected to the acquisition clock.
RESET
Global synchronous reset, active high.

Properties

Property window

X Integer Bits X_BitsInt

Number of INTEGER bits of X (the sign, when present, uses one of them).

Number of INTEGER bits of the operand X (1 to 64). When the port is SIGNED one of these bits carries the sign.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

X Fractional Bits X_BitsFract

Number of FRACTIONAL bits of X, i.e. how many bits sit to the right of the binary point. Total width = integer + fractional bits.

Number of FRACTIONAL bits of the operand X (0 to 64), i.e. the bits to the right of the binary point. Total port width = integer + fractional bits.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

X Sign X_Sign

Select whether X is a signed (two’s complement) or unsigned quantity.

Arithmetic type of X:

  • SIGNED – two’s complement, range $[-2^{N_{int}-1}, 2^{N_{int}-1})$
  • UNSIGNED – non negative only, range $[0, 2^{N_{int}})$

Default: SIGNED

Options: UNSIGNED SIGNED

Y Integer Bits Y_BitsInt

Number of INTEGER bits of Y (the sign, when present, uses one of them).

Number of INTEGER bits of the operand Y (1 to 64). When the port is SIGNED one of these bits carries the sign.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Y Fractional Bits Y_BitsFract

Number of FRACTIONAL bits of Y, i.e. how many bits sit to the right of the binary point. Total width = integer + fractional bits.

Number of FRACTIONAL bits of the operand Y (0 to 64), i.e. the bits to the right of the binary point. Total port width = integer + fractional bits.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Y Sign Y_Sign

Select whether Y is a signed (two’s complement) or unsigned quantity.

Arithmetic type of Y:

  • SIGNED – two’s complement, range $[-2^{N_{int}-1}, 2^{N_{int}-1})$
  • UNSIGNED – non negative only, range $[0, 2^{N_{int}})$

Default: SIGNED

Options: UNSIGNED SIGNED

Y is TM B_IsTM

YES: operand Y is time multiplexed like X. NO: it is a single scalar value broadcast to every TM slot.

  • YES – operand Y is time-multiplexed and is consumed slot by slot
  • NO – operand Y is a single scalar broadcast to every TM slot

Default: YES

Options: NO YES

MAG Integer Bits MAG_BitsInt

Number of INTEGER bits of MAG (the sign, when present, uses one of them).

Number of INTEGER bits of the result MAG (1 to 64). When the port is SIGNED one of these bits carries the sign.

Default: 17

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

MAG Fractional Bits MAG_BitsFract

Number of FRACTIONAL bits of MAG, i.e. how many bits sit to the right of the binary point. Total width = integer + fractional bits.

Number of FRACTIONAL bits of the result MAG (0 to 64), i.e. the bits to the right of the binary point. Total port width = integer + fractional bits.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

MAG Sign MAG_Sign

Select whether MAG is a signed (two’s complement) or unsigned quantity.

Arithmetic type of MAG:

  • SIGNED – two’s complement, range $[-2^{N_{int}-1}, 2^{N_{int}-1})$
  • UNSIGNED – non negative only, range $[0, 2^{N_{int}})$

Default: SIGNED

Options: UNSIGNED SIGNED

PHASE Integer Bits PHASE_BitsInt

Number of INTEGER bits of PHASE (the sign, when present, uses one of them).

Number of INTEGER bits of the result PHASE (1 to 64). When the port is SIGNED one of these bits carries the sign.

Default: 17

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

PHASE Fractional Bits PHASE_BitsFract

Number of FRACTIONAL bits of PHASE, i.e. how many bits sit to the right of the binary point. Total width = integer + fractional bits.

Number of FRACTIONAL bits of the result PHASE (0 to 64), i.e. the bits to the right of the binary point. Total port width = integer + fractional bits.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

PHASE Sign PHASE_Sign

Select whether PHASE is a signed (two’s complement) or unsigned quantity.

Arithmetic type of PHASE:

  • SIGNED – two’s complement, range $[-2^{N_{int}-1}, 2^{N_{int}-1})$
  • UNSIGNED – non negative only, range $[0, 2^{N_{int}})$

Default: SIGNED

Options: UNSIGNED SIGNED

TM Factor TimeMultiplexing

Time multiplexing factor

Time multiplexing factor: 4, 8, 16 or 32 samples packed per port. One operator instance is generated per slot.

Default: 4

Options: 4 8 16 32

Rounding Rounding

ROUND: round to nearest when discarding fractional bits. TRUNCATE: drop them (cheaper, adds a DC bias).

  • ROUND – round to nearest when discarding fractional bits
  • TRUNCATE – discard them (cheaper, introduces a negative bias)

Default: ROUND

Options: TRUNCATE ROUND

Saturation EnableSaturation

YES: clip to the largest representable output value on overflow. NO: wrap around (cheaper, but overflow changes sign).

  • YES – clip to the largest representable output value on overflow
  • NO – wrap around modulo the output width

Default: YES

Options: NO YES

Status Flags StatusFlags

YES: the block exposes three extra 1-bit outputs, valid together with OUT_DV – NAN (the result is mathematically undefined for the operands presented, or the operand had to be clamped into the convergence domain of the algorithm), OL (overflow: the true result left the output format and was saturated), and UL (underflow: the true result was not zero but requantized to zero). NO: the pins are not generated and the logic that produces them is not synthesised.

Default: YES

Options: NO YES

Angle Unit AngleUnit

Unit used by the angle port: RADIANS, TURNS (1.0 = full circle) or DEGREES.

Unit of the angle port:

  • RADIANS – the usual $[-\pi, \pi]$ convention
  • TURNS – 1.0 is a full circle; this is the native internal unit, so it avoids the multiplication by $1/2\pi$ and is the most accurate choice
  • DEGREES – 360.0 is a full circle

Default: RADIANS

Options: RADIANS TURNS DEGREES

CORDIC Iterations CordicIterations

Number of CORDIC rotations. Each iteration adds roughly one bit of accuracy and one adder stage; there is no point going far beyond the number of output fractional bits.

Number of CORDIC iterations (8 to 32). Roughly one bit of accuracy per iteration; there is little benefit in exceeding the number of fractional bits of the result.

Default: 20

Options: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Pipeline Length PipelineLength

Fixed latency of the block, in clock cycles. More stages ease timing closure. Ignored in SERIAL mode, where the latency is set by the iteration count.

Fixed latency of the block in clock cycles (1 to 8). Higher values ease timing closure without changing the numerical result.

Default: 10

Options: 1 2 3 4 5 6 7 8

Functional description

$$ \mathrm{MAG} = \sqrt{X^2+Y^2}, \quad \mathrm{PHASE} = \operatorname{atan2}(Y, X) $$

where

  • X – input operand, format $Q_{X_BitsInt.X_BitsFract}$
  • Y – input operand, format $Q_{Y_BitsInt.Y_BitsFract}$
  • MAG – result, format $Q_{MAG_BitsInt.MAG_BitsFract}$
  • PHASE – result, format $Q_{PHASE_BitsInt.PHASE_BitsFract}$

Fixed-point format

A value with $N_{int}$ integer bits and $N_{frac}$ fractional bits is stored on $N_{int} + N_{frac}$ bits and represents

$$ \text{value} = \frac{\text{raw integer}}{2^{N_{frac}}} $$

When the operand is SIGNED, one of the integer bits carries the sign (two’s complement). Each port is configured independently, so it is perfectly legal to feed a $Q_{16.0}$ signal and a $Q_{2.14}$ coefficient into the same block.

Implementation

One circular CORDIC vectoring iteration produces both outputs, so this costs about half of the two separate blocks. Each output has its own Q format.

The CordicIterations property sets the number of rotations. Each iteration is worth roughly one extra bit of accuracy and costs one adder stage, so there is no benefit in setting it much higher than the number of fractional bits of the result.

Rounding and overflow

Two properties control how the internal full precision result is reduced to the output format:

  • Rounding – ROUND rounds to nearest when fractional bits are discarded, TRUNCATE simply drops them. Truncation is cheaper but introduces a systematic negative bias, which accumulates in a long processing chain.
  • Saturation – YES clips to the largest representable value, NO wraps around. Wrapping turns a small overflow into a full-scale sign flip, so saturation is strongly recommended for signal processing.

Time multiplexing

The wide ports carry TM samples packed from the least significant bits up:

    bits [W-1 : 0]      -> slot 0
  bits [2W-1 : W]     -> slot 1
  ...
  bits [TM*W-1 : (TM-1)*W] -> slot TM-1

where W is the width of a single sample. One operator instance is generated per slot, so the resource usage scales with the TM factor while the throughput stays one full set of samples per clock.

Latency

The PipelineLength property fixes the latency of the block in clock cycles (1 to 8). Raising it helps timing closure at high clock rates and does not change the numerical result. The symbol reports the configured latency.

Typical use cases

  • I/Q to envelope and phase conversion
  • Polar representation for magnitude thresholding
  • Front end of a phase locked loop