Variable Delay Group [TM]
Time-multiplexed programmable delay line with runtime-adjustable delay for all TM phases. All phases share the same DELAY value and are delayed identically. Uses block RAM for efficient storage. Provides 1 clock cycle inherent latency plus the programmed delay.
Introduction
This block implements a time-multiplexed programmable delay line where all TM phases are delayed by the same runtime-controlled amount. The DELAY input applies globally to all TM phases.
$$ \mathrm{OUT}_i(n) = \mathrm{IN}_i(n - D - 1), $$
where $i$ is the TM phase index and $D$ is the DELAY input value.
Pin Description
Properties
Set the amount of memory to reserve for this delay line
Maximum delay capacity. Allowed values: 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32756, 65536. Total RAM = MaxDelayValue × BusWidth × TMFactor bits.Default: 1024
Options: 64 128 256 512 1024 2048 4096 8192 16384 32756 65536
Set the size in bits of the signal to be delayed
Bit width per TM phase (not total). Range: 1-1024. Total width = BusWidth × TMFactor.Default: 1
Range: 1 – 1024
Time Multiplexing factor
TM Factor (number of phases). Allowed values: 4, 8, 16, 32. Each phase uses independent storage in RAM.Default: 4
Options: 4 8 16 32
Functional description
The component uses block RAM to store all TM phases. Unlike Variable Delay Fine TM, this variant delays entire TM groups (all phases together) rather than individual samples.
Key characteristics
- Shared delay: All TM phases use the same DELAY value
- Group delay: Delays entire TM vectors, not individual phase samples
- Total latency: DELAY + 1 clock cycles
- TM factors: Supports 4, 8, 16, or 32 phases
Timing
Same as non-TM Variable Delay: DELAY + 1 clock cycles for all phases.
Typical use cases
- Multi-channel programmable buffering
- TM pipeline balancing with runtime control
- Parallel data stream synchronization