ISIS PSD COEF TM

Introduction link

Principle of Operation link

ISIS PSD COEF TM is generated from isispsdcoeff.cpp, which is isispsd.cpp with the filter coefficients lifted from compile-time constants to function arguments. Everything else — the 4-lane time-multiplexed input, the lane-average discriminator, the PSD threshold with its over-threshold counter, the 128-entry pre-trigger delay line, the four parallel integrators and the event output — is identical. Read the ISIS PSD TM page first; this page documents only what is different.

The low-pass section is still the scattered look-ahead form of a 2nd-order IIR,

$$ y[n] ;=; \sum_{k=0}^{6} b_k,x[n-k] ;-; a_1,y[n-3] ;-; a_2,y[n-6] $$

but now $a_1, a_2$ arrive on LP_A1, LP_A2 and $b_0 \dots b_6$ on LP_B0 … LP_B6.

Each coefficient pin is 18 bit wide and carries an ap_fixed<18,2> value: signed, two integer bits, sixteen fractional bits. To program a real coefficient $c$ drive the two’s complement of

$$ \mathrm{raw} ;=; \mathrm{round}!\left(c \times 65536\right), \qquad -2 \le c < 2 $$

so the resolution is $2^{-16} \approx 1.5\times10^{-5}$.

Pin Description link

Properties link

⚙️ Detailed Operation link

What changed with respect to ISIS PSD TM link

Everything else — lane unpacking (lane 0 in the low bits, oldest sample), the (x0+x1+x2+x3) >> 2 lane average compared with TH, the 6553-high discriminator pulse, the OVR_SAMPLES consecutive-clock condition on TH_PSD, the PRETRG delay line limited to 127 clocks, the four-slot integrator with its Stop Integral / Continue pile-up modes, the timestamp + 4 × PRETRG event stamp and the Internal / External ratio — behaves exactly as described on the ISIS PSD TM page.

Reference coefficient set link

The values that are hard-coded in the non-programmable block are the natural starting point for the programmable one:

The sign convention is the one used in the source: the two feedback terms are subtracted (- a1·y[n-3] - a2·y[n-6]), so LP_A1 is negative for this reference set.

The high-pass section is not programmable link

isispsd_coeff() declares the arguments hp_a1, hp_b0, hp_b1, hp_b2, hp_b3 and passes them to highpassfilter(), but the body of highpassfilter() never uses them — it still reads the local constant arrays:

  const t_filter_coef hp_a[] = { 1, -0.8599680957679054 };
const t_filter_coef hp_b[] = { 0.97547839, -0.0478406, -0.04549434, -0.88214345 };
...
hp_y = hp_b[0]*x + hp_b[1]*hp_x1 + hp_b[2]*hp_x2 + hp_b[3]*hp_x3 - hp_a[1]*hp_y3;
  

Designing a coefficient set link

The shaping chain turns a rectangular discriminator pulse into a signal whose amplitude grows with the width of that pulse; TH_PSD then separates the species. When you retune the low-pass section, keep in mind:

• the section is written in scattered look-ahead form, so the feedback taps are at $n-3$ and $n-6$, not at $n-1$ and $n-2$. A conventional biquad $(a_1, a_2)$ pair cannot be dropped in unchanged — it must be transformed to the 3-fold-scattered equivalent, which is also why there are seven $b_k$ for a 2nd-order response;
• the accumulator type is ap_fixed<24,16>, i.e. 16 integer bits with 8 fractional bits, so a set with a large DC gain will saturate before the output reaches MON_LP;
• the coefficients are declared ap_stable: they are meant to be static during acquisition. Change them while the input is quiet.

Generated hardware and build link

Identical to ISIS PSD TM except for the top function name:

• source written to HLS/<unique>/isispsd_coeff.cpp with the INTERNAL_RATIO / STOP_INTEGRAL_ON_PILEUP defines prepended;
• hls_compile.tcl runs csynth_design with set_directive_top -name <unique> isispsd_coeff, a clock period of floor(1000000 / AcquisitionClockFreq) ns (4 ns on the NI DAQ121’s 250 MHz CLK_ACQ), and merges the VHDL into HDL/pcores/<unique>.vhd;
• the IP name is isispsd_coeff_<8 letters>, the letters being an MD5 of (component name, ADC BITS, Time Mux, Ratio) — Pileup is not in the hash, so two instances differing only in that property share one IP;
• ap_clk is tied to the acquisition clock (there is no CLK pin), ap_rst to the global reset when RESET is left open;
• the block requires a license and is offered only on the NI DAQ121 (board GUID 10B906F8-657F-4C13-A697-4637BE6DEC27);
• CompileHDL aborts silently when Vitis HLS is not found and the build is not remote.

There is no CompileMMC / CompileSDK content: the block has no software registers, so the coefficients must be driven from constant or register blocks on the schematic.

Resources & Timing link

• Latency: Declared block latency: 20 clocks with Ratio = External, 55 clocks with Ratio = Internal

• Throughput: One 64-bit word (4 samples) per clock, II = 1; at most one event per clock on EVNT_VALID

• 4 concurrent integrators; a 5th simultaneous event is dropped without any flag.
• 128-entry × 64-bit pre-trigger delay line, so PRETRG must stay below 128.
• Coefficient pins are ap_fixed<18,2> (raw = value × 65536); filter states ap_fixed<24,16>.
• Nine of the fourteen coefficient inputs are effective; the five high-pass ones are not.