Xilinx
TM
Block Preview

Introduction

This block performs IEEE 754 floating-point multiplication using the Xilinx Floating Point IP core. The component supports Time Multiplexing (TM): multiple parallel computation units (phases) share the same clock cycle, enabling high sample rates with predictable latency.

On every rising edge of CLK, if A_CE = 1, B_CE = 1, and READY_IN = 1, the operator performs

$$ \mathrm{F}(n) = \mathrm{A}(n) \times \mathrm{B}(n), $$

where all operands are IEEE 754 floating-point values. The TM Factor property determines how many parallel instances are instantiated.

Pin Description

A Input Variable bit TM
Floating-point input A, always TM. Width: (Exponent + Mantissa) × TMFactor
Default: Must be connected
A_CE Input 1 bit BIT
Input A clock enable, active high.
B Input Variable bit TM

Floating-point input B.

  • If B is TM = YES: TM bus of width same as A
  • If B is TM = NO: Scalar replicated to all phases
Default: Must be connected
B_CE Input 1 bit BIT
Input B clock enable, active high.
READY_IN Input 1 bit BIT
Downstream ready signal. Default ‘1’ if not connected.
CLK Input 1 bit BIT
Global clock for all TM phases.
Default: Default Board Clock
F Output Variable bit TM
Floating-point output, always TM. Each phase produces A × B. Valid after 9 clock cycles.
DV Output 1 bit BIT
Data Valid output, active high.
A_READY Output 1 bit BIT
Input A ready output.
B_READY Output 1 bit BIT
Input B ready output.

Properties

Property window

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Number of time-multiplexed phases (1 – 32).

Default: 4

Range: 1 – 32

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Floating-point format:

  • Single → 32-bit (8 exp + 24 mantissa)
  • Double → 64-bit (11 exp + 53 mantissa)

Default: Single

Options: Single Double

B is TM B_IsTM

Select if input B is Time Multiplexed or the same for all phases

  • YES → B is TM (each phase gets its slice)
  • NO → B is scalar (replicated to all phases)

Default: YES

Options: NO YES

DSP Usage DSPUsage

DSP Usage. Single precision: No [0], Medium [1], Full[2], Max[3]. Double precision: No[0], Medium [9], Full[10], Full[11]

DSP slice usage:

  • No_Usage, Medium_Usage, Full_Usage Single: No [0], Medium [3], Full[4] Double: No[0], Medium [11], Full[16]

Default: Full_Usage

Options: No_Usage Medium_Usage Full_Usage Max_Usage

Functional description

The component wraps the Xilinx Floating Point IP (operation type: Multiply) and replicates it N times (where N = TM Factor) to support time-multiplexed data streams.

Input modes

  • Input A is always TM, with width (Exponent + Mantissa) × TMFactor
  • Input B can be either:
    • TM mode (B is TM = YES): Same width as A, each phase gets its slice
    • Broadcast mode (B is TM = NO): Single value replicated to all phases

Output

  • Output F is always TM, with the same width as input A

Mathematical background

IEEE 754 floating-point multiplication with proper rounding and special case handling:

$$ x \times y = \text{round}(x \times y) $$

Special cases:

  • $x \times 1 = x$
  • $x \times 0 = 0$
  • $\infty \times 0 = \text{NaN}$
  • $\infty \times x = \infty$ (for finite $x \neq 0$)
  • $\text{NaN} \times x = \text{NaN}$

Timing

The Xilinx Floating Point IP has a fixed latency of 9 clock cycles per phase:

Property Latency (clock cycles)
Multiplication 9

DSP Usage

  • Single precision: No [0], Medium [3], Full[4]
  • Double precision: No[0], Medium [11], Full[16]

Typical use cases

  • Gain control and scaling
  • FIR filter tap multiplication
  • Complex number multiplication
  • Power calculations
  • Modulation