Block Preview

Introduction

This block converts parallel data to serial by loading a parallel word and shifting it out one bit per clock cycle. Useful for interfacing with serial communication protocols.

Pin Description

DATA Input Variable bit BIT VECTOR
Parallel input data. Width: Parallel Width (2-65535 bits). Loaded when LE=1.
Default: Must be connected
SERIAL_IN Input 1 bit BIT
Serial input (1-bit). Concatenated after DATA if CE remains HIGH.
CE Input 1 bit BIT
Clock enable (1-bit). Must stay HIGH during serialization.
Default: Must be connected
LE Input 1 bit BIT
Load enable (1-bit). Loads DATA into shift register when HIGH.
Default: Must be connected
CLK Input 1 bit BIT
Clock signal for shift operations.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset.
Default: Must be connected
SERIAL_OUT Output 1 bit BIT
Serial output (1-bit). Shifts out one bit per clock cycle.

Properties

Property window

Bit Order BitOrder

Set the order of the serialized bit

Bit transmission order: MSB FIRST or LSB FIRST.

Default: MSB FIRST

Options: MSB FIRST LSB FIRST

Parallel Width BusWidth

Set the size in bits of the input parallel word width

Parallel word width. Range: 2-65535 bits.

Default: 16

Range: 2 – 65535

Functional description

Operation sequence:

  1. Assert LE=1 to load parallel DATA
  2. Keep CE=1 while shifting out bits on SERIAL_OUT
  3. Optionally provide additional bits via SERIAL_IN after parallel data finishes

Bit order

  • MSB FIRST: Most significant bit transmitted first
  • LSB FIRST: Least significant bit transmitted first

Timing

Latency: 1 clock cycle to first bit output. Shift rate: 1 bit per clock cycle.

Typical use cases

  • Serial communication interfaces (SPI, UART)
  • Bit-serial arithmetic
  • Data width conversion