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Introduction

The pipelined divider performs fixed-point division with configurable precision. It computes:

$$ \mathrm{OUT} = \frac{\mathrm{Q}}{\mathrm{D}} \times 2^{F} $$

where Q is the dividend, D is the divisor, and F is the fractional part width. The result includes both integer and fractional components, enabling precise fixed-point arithmetic.

The divider uses AXI-Stream handshake protocol with valid signals (DV_IN, DV_OUT) for data flow control.

Pin Description

Q Input Variable bit BIT VECTOR
Dividend input (numerator). Width: Dividend Size (8, 16, 24, 32, 40, 48, 56, or 64 bits). Arithmetic type set by Operand Type.
Default: Must be connected
D Input Variable bit BIT VECTOR
Divisor input (denominator). Width: Divider Size (8, 16, 24, 32, 40, 48, 56, or 64 bits). Arithmetic type set by Operand Type.
Default: Must be connected
DV_IN Input 1 bit BIT
Data valid input signal. When high, indicates valid data on Q and D inputs.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable, active high. Only present when Latency is not “None”. When low, pipeline stages hold their current state.
Default: 1
CLK Input 1 bit BIT
Clock input. Only present when Latency is not “None”. Drives pipeline registers.
Default: Default Board Clock
OUT Output Variable bit BIT VECTOR
Quotient output (Q/D with fractional precision). Width: Dividend Size + Fractional Part Size.
DV_OUT Output 1 bit BIT
Data valid output signal. Indicates valid result on OUT.

Properties

Property window

Operand Type SignedUnsigned

Select between signed and unsigned operands

Arithmetic type for operands:

  • Signed: Two’s-complement representation
  • Unsigned: Non-negative integers only

Default: Signed

Options: Signed Unsigned

Dividend Size InputQBitCount

Set the number of bits for Dividend. Output Size will be Dividend + Fractional Part

Bit width of dividend input Q. Allowed values: 8, 16, 24, 32, 40, 48, 56, 64.

Default: 16

Options: 8 16 24 32 40 48 56 64

Divider Size InputDBitCount

Set the number of bits for Divider

Bit width of divisor input D. Allowed values: 8, 16, 24, 32, 40, 48, 56, 64.

Default: 16

Options: 8 16 24 32 40 48 56 64

Fractional Part Size FractPartBitCount

Set the number of bits for fractional part. Output Size will be Quotient + Fractional Part

Bit width of fractional part in output. Allowed values: 8, 16, 24, 32, 40, 48, 56, 64. Output width = Dividend Size + Fractional Part Size.

Default: 16

Options: 8 16 24 32 40 48 56 64

Latency Latency

Select the pipeline length for the divider. Longer pipeline means better performance but higher area used in the FPGA.

Pipeline configuration:

  • Max: Maximum pipeline depth, highest frequency
  • Medium: Half pipeline depth
  • Short: Quarter pipeline depth
  • Very Short: Minimal pipeline
  • None: Combinatorial (no pipeline)

Default: Max

Options: Max Medium Short Very Short None

Functional description

The component implements a fully-pipelined divider using the Xilinx div_gen IP core. The division operates on fixed-point numbers with separate control over:

  • Dividend (Q): Input width 8-64 bits
  • Divisor (D): Input width 8-64 bits
  • Fractional part (F): Output fractional width 8-64 bits

Output format

The output width is:

$$ W_{\text{out}} = W_{\text{dividend}} + W_{\text{fractional}} $$

This allows representing quotients with configurable precision.

Pipeline configuration

The Latency property controls the pipeline depth:

Latency Mode Pipeline Stages
Max $W_{\text{out}} + 2$
Medium $W_{\text{out}} / 2 + 2$
Short $W_{\text{out}} / 4 + 2$
Very Short $\min(W_{\text{out}}, 2)$
None 0 (combinatorial)

Longer pipelines achieve higher clock frequencies but increase latency.

AXI-Stream interface

The component uses AXI-Stream protocol:

  • DV_IN: Valid signal for input data
  • DV_OUT: Valid signal for output data
  • CE: Clock enable (only in pipelined modes)

Typical use cases

  • Fixed-point arithmetic in DSP algorithms
  • Normalization and calibration
  • Reciprocal calculation
  • Rate computation in control systems