Introduction

This tutorial demonstrates how to configure the DT5550W board with Petiroc ASIC piggyback for Silicon Photomultiplier (SiPM) readout and photon counting applications.

About DT5550W with Petiroc

The DT5550W is a complete readout system based on Weeroc ASICs. The Petiroc (Positron Emission Time Imaging ReadOut Chip) is specifically designed for SiPM array readout and provides:

  • 32 channels per ASIC (up to 128 channels with 4 ASICs)
  • Charge measurement and time measurement on each channel
  • Individual trigger outputs per channel
  • Integrated discriminators with adjustable thresholds
  • On-board HV generation for SiPM bias (20-85V)

What You’ll Learn

  • Configuring Petiroc ASIC parameters
  • Controlling on-board high voltage for SiPM bias
  • Implementing trigger counters in FPGA
  • Testing photon counting with Resource Explorer
  • Using Weeroc configuration tools in SCI-Compiler

Hardware Requirements

For this tutorial you need:

  • DT5550W Petiroc board (with Petiroc piggyback)
  • SiPM matrix (e.g., Hamamatsu S13361-3050AE-08)
  • Dark box (provided with DT5550W kit)
  • Light pulser (e.g., CAEN SP5601 or equivalent)
  • Optical fiber
  • USB 3.0 cable for communication
  • JTAG cable for FPGA programming

Hardware Setup

Experimental Setup

The photon counting experiment setup consists of:

Figure 1: DT5550W Petiroc experimental setup with SiPM, dark box, and light pulser

Setup description:

  1. SiPM matrix is installed on the Petiroc piggyback board
  2. Dark box shields the SiPM from ambient light
  3. Light pulser generates optical pulses via fiber
  4. Optical fiber delivers light to the SiPM
  5. DT5550W processes signals and counts triggers

Signal Flow 

  Light Pulser → Optical Fiber → SiPM → Petiroc ASIC → FPGA Counters

When light hits the SiPM:

  • SiPM generates electrical pulse
  • Petiroc ASIC discriminates signal above threshold
  • Trigger output transitions from 0→1
  • FPGA counter increments
  • Count value stored in register

Firmware Design Overview

Project Goals

The firmware implements three main functions:

  1. Configure the Petiroc ASIC (thresholds, polarity, mode)
  2. Control high voltage generator (SiPM bias)
  3. Count triggers and store in registers (one counter per channel)

Block Diagram

SCI-Compiler provides dedicated blocks for Weeroc ASICs in the Board menu.

Figure 2: Weeroc ASIC blocks in SCI-Compiler

Available example: SCI-Compiler includes this project as an example:

  • File → Open Example → DT5550W → Petiroc Photon Counting

Step 1: Petiroc Slow Control Block

The Petiroc Slow Control block manages ASIC configuration.

Block Configuration

Figure 3: Petiroc Slow Control block properties

Parameters:

  • ASIC to configure: Select which Petiroc ASIC (if multiple)
  • Default configuration: Configuration applied at boot/reset
  • Default monitor config: Monitoring settings

This is a memory-mapped block accessible via USB using SciSDK or Resource Explorer.

Opening Configuration Tool

Press the Edit button to open the Weeroc Configuration Tool:

Figure 4: Weeroc Petiroc configuration interface

Configuration options:

  • Charge threshold (per channel or global)
  • Time threshold (per channel or global)
  • Polarity (positive/negative)
  • Trigger mode and latching
  • Channel enable/disable
  • OR logic configuration

Step 2: Counter Blocks

Each processing channel counts triggers from the ASIC.

Counter Implementation

Figure 5: Counter blocks for each trigger channel

Function:

  • Each Petiroc trigger output connects to a counter
  • Counter increments on 0→1 transition
  • Count value stored in a register
  • Register mapped to USB for readout

Example:

  • C1 register → Counts from ASIC channel 1
  • C2 register → Counts from ASIC channel 2
  • etc.

Step 3: Memory Mapping

Assign addresses to registers and peripherals.

Memory Map Configuration

Figure 6: Memory mapping tab

Options:

  • Manual address: Enter specific address in “PHY Hex” column
  • Auto Assign: Click button to automatically allocate addresses
  • Lock address: Check “Manual Assigned” to prevent auto-assign override

Output: A RegisterFile.json is generated in the project’s library folder during compilation.

Step 4: Compile and Program

Compilation

  1. Click Compile button in the Home toolbar
  2. Compilation takes 10-20 minutes
  3. Upon success, a bitstream is generated

Programming

  1. Connect DT5550W via:
    • USB 3.0 (communication)
    • JTAG USB (programming)
  2. Power on the board
  3. Click Program FPGA in SCI-Compiler
  4. Wait for “Target device programmed successfully”

Testing with Resource Explorer

Launch Resource Explorer

Resource Explorer allows you to interact with the firmware without writing code.

Figure 7: Opening Resource Explorer

Connect to Board

  1. Select DT5550W-PETIROC from board list
  2. Click Scan to detect connected boards
  3. Select correct Serial Number
  4. Verify JSON file path matches your project
  5. Click Connect

Figure 8: Resource Explorer connection settings

Discovered Resources

After connection, Resource Explorer enumerates:

Figure 9: Enumerated resources

  • Registers (C1, C2, C3… counter registers)
  • PetirocCfg (ASIC configuration)
  • HVcontrol (High voltage controller)

Step 5: Configure High Voltage

Configure the on-board HV generator for SiPM bias.

HV Controller

  1. Right-click on i2c_master_0 under HVcontrol
  2. Select Open Configuration
  3. Set parameters:
    • HV Voltage: 54V (adjust based on your SiPM)
    • Enable: Check to turn on HV
  4. Click Set or Update

Figure 10: High voltage configuration panel

Monitoring: Click Update to view:

  • Current HV voltage
  • HV current draw
  • SiPM temperature sensor reading

Warning: Ensure SiPM is properly connected before enabling HV. Consult SiPM datasheet for correct bias voltage.

Step 6: Configure Petiroc ASIC

Set discrimination thresholds and operating mode.

Open Petiroc Configuration

Right-click on PetirocCfg → Open Configuration

Figure 11: Petiroc configuration interface

Generate Configuration

Click Generate to open the full ASIC configuration tool.

Figure 12: Detailed Petiroc configuration

Set the following parameters:

Parameter Value Notes
Charge Threshold 300 Lower value = higher threshold (positive polarity)
Time Threshold 200 Lower value = higher threshold (positive polarity)
Polarity Positive Match SiPM output polarity
Trigger Latch Disabled No latch on trigger
Charge OR32 Disabled Individual channel triggers
Time OR32 Disabled MUST disable due to silicon bug

Important: In positive polarity mode, lower threshold values correspond to higher discrimination levels. This is counter-intuitive but correct for the Petiroc ASIC.

Advanced Settings

Figure 13: Advanced configuration options

Configure:

  • Per-channel threshold adjustments
  • Channel enable/disable masks
  • DAC settings
  • Preamp gain

Apply Configuration

  1. Click Generate in the configuration tool
  2. The bitstream is displayed in the text field
  3. Click Send to program the ASIC

Example bitstream (for reference):

  0000000000000000000000000000000000000001100000001100000001100000...

You can copy/paste this bitstream for use in SDK applications.

Figure 14: Sending configuration to ASIC

Step 7: Read Counter Registers

Monitor photon counts in real-time.

Open Counter Registers

  1. In Resource Explorer, expand Registers
  2. Right-click on C1 (channel 1 counter)
  3. Select Set/Get or Monitor
  4. Repeat for C2 (channel 2 counter)

Configure Auto-Read

For continuous monitoring:

  • Set Auto Read Mode to 50 ms
  • Set Format to Decimal
  • Click Start on both registers

Figure 15: Monitoring counter registers

Step 8: Observe Photon Counting

Test with Light Pulser

  1. Turn on the light pulser
  2. Adjust light intensity
  3. Observe counter values increasing

Expected results:

  • C2 counter: High count rate (SiPM pixel receiving light)
  • C1 counter: Low count rate (pixel receiving little/no light)

The SiPM pixels are at different positions in the matrix, so light distribution varies.

Adjust Threshold

Experiment with threshold settings:

  1. Open Petiroc configuration again
  2. Change Charge Threshold to a different value (e.g., 200)
  3. Click Generate and Send
  4. Observe counter behavior changes

Figure 16: Counter response with different threshold settings

Lower threshold value (e.g., 200) = Higher discrimination → Fewer counts, only bright pulses Higher threshold value (e.g., 400) = Lower discrimination → More counts, including noise

Understanding the Design

Trigger Counting Principle 

  SiPM Pulse → Petiroc Discriminator → Trigger (0→1) → Counter++

Each trigger transition increments the counter:

  • Rising edge (0→1) detected by counter block
  • Counter value increments by 1
  • Value continuously written to register
  • Register readable via USB

ASIC Configuration Flow 

  SCI-Compiler → Generate Bitstream → Slow Control Block → I2C → Petiroc ASIC

Configuration is stored in the ASIC’s internal registers and persists until:

  • Power cycle
  • Manual reconfiguration
  • ASIC reset

High Voltage Control 

  Resource Explorer → I2C Master → HV Controller IC → DC-DC Converter → SiPM Bias

The DT5550W includes:

  • Programmable HV DAC (20-85V range)
  • Current monitoring
  • Temperature sensing
  • Software-controlled enable/disable

Typical Applications

Photon Counting

  • Dark count measurement
  • Single photon detection
  • Scintillator readout (LYSO, NaI, BGO)
  • Quantum optics experiments

PET/SPECT Imaging

  • Positron Emission Tomography
  • Single Photon Emission Computed Tomography
  • Time-of-Flight (ToF) PET
  • Multi-channel coincidence

High Energy Physics

  • Calorimeter readout
  • Tracker systems
  • Timing detectors
  • Cherenkov light detection

Medical Physics

  • Gamma cameras
  • Dose monitoring
  • Radiation therapy
  • Nuclear medicine

Advanced Topics

Multi-ASIC Configurations

DT5550W supports up to 4 Petiroc ASICs (128 channels total):

  • Each ASIC configured independently
  • Shared HV distribution
  • Individual trigger outputs
  • Synchronized readout

Time Measurement

Petiroc provides both charge and time outputs:

  • Use Oscilloscope block to capture analog outputs
  • Implement TDC for precise timing
  • Measure Time-over-Threshold (ToT)
  • Calculate Time-of-Arrival (ToA)

Energy Measurement

Add processing blocks:

  • Charge Integration (QDC) for energy
  • Spectrum block for MCA functionality
  • Baseline restoration
  • Pile-up rejection

List Mode Acquisition

Record event-by-event data:

  • Timestamp per trigger
  • Charge value
  • Time value
  • Channel ID
  • Store in List endpoint for streaming to PC

Troubleshooting

No Counts Observed

Problem: Counters remain at zero

Solutions:

  • Verify light pulser is on and fiber connected
  • Check HV is enabled and at correct voltage
  • Ensure ASIC configuration was sent successfully
  • Lower threshold (increase threshold value in positive mode)
  • Verify SiPM is properly installed and connected

All Channels Counting (Too Many Counts)

Problem: Excessive count rate on all channels

Solutions:

  • Check for light leaks in dark box
  • Raise threshold (decrease threshold value)
  • Reduce HV to lower SiPM gain
  • Check for electrical noise/crosstalk

HV Not Stable

Problem: HV voltage fluctuates or doesn’t reach setpoint

Solutions:

  • Check SiPM load (current draw)
  • Verify board power supply is adequate
  • Ensure temperature is stable
  • Check for short circuits on SiPM connections

ASIC Configuration Fails

Problem: Cannot send configuration to Petiroc

Solutions:

  • Verify firmware is programmed correctly
  • Check USB connection
  • Restart Resource Explorer
  • Try manual configuration via registers

Summary

This tutorial covered DT5550W Petiroc photon counting:

Topic Covered
Hardware setup SiPM, dark box, light pulser configuration
Firmware design Petiroc Slow Control, counters, registers
ASIC configuration Thresholds, polarity, trigger mode
HV control Bias voltage, monitoring, safety
Testing Resource Explorer, counter readout
Troubleshooting Common issues and solutions

Next steps:

  • Experiment with different SiPM types
  • Add energy and timing measurements
  • Implement coincidence logic
  • Develop custom SDK applications with SciSDK
  • Explore multi-ASIC configurations

The DT5550W with Petiroc ASIC provides a complete, flexible platform for SiPM-based detector readout without requiring HDL programming!