TM

Introduction

The block performs time-multiplexed floating-point to fixed-point conversion across multiple data streams. On every rising edge of CLK, when IN_DV = 1, the converter computes

$$ \mathrm{OUT}_i(n) = \text{fixed}(\mathrm{IN}_i(n)), \quad i = 0, \ldots, \text{TM}-1, $$

where each subscript $i$ represents a different TM phase, TM is the time-multiplexing factor (4, 8, 16, or 32), and the input follows IEEE-754 single (32-bit) or double (64-bit) precision format.

The input can be either time-multiplexed (converting multiple channels in parallel) or scalar (broadcasting a single floating-point value to all TM output phases).

This component enables efficient multi-channel conversion for applications requiring the efficiency and determinism of fixed-point arithmetic after floating-point processing.

Pin Description

IN Variable bit

Floating-point input (IEEE-754), can be time-multiplexed or scalar. If Input is TM = YES: Width: (32 bits for Single or 64 bits for Double) × TM Factor Contains TM phases: [IN0, IN1, …, IN(TM-1)] If Input is TM = NO: Width: 32 bits (Single) or 64 bits (Double) Single value broadcast to all output phases

Format: IEEE-754 single or double precision.

Default: Must be connected
IN_DV
Data Valid for input, active high. When high, input IN contains valid floating-point data to be converted. Can be tied to ‘1’ for continuous streaming.
CLK
Global clock. Each rising edge processes one TM phase through the converter. Connected to system acquisition clock.
RESET
Synchronous reset, active high. Clears all pipeline registers and internal state.
OUT

Time-multiplexed fixed-point output (always TM). Width: (Integer Bits + Fractional Bits) × TM Factor. Contains converted results: [OUT0, OUT1, …, OUT(TM-1)]. Valid when OUT_DV = 1.

Format: Signed fixed-point with configurable integer and fractional parts.

OUT_DV
Data Valid output, active high. Indicates when OUT contains valid fixed-point results. Asserts after Pipeline Length × TM clock cycles from input valid.

Properties

FloatPrecision FloatPrecision

Input floating-point precision format:

  • SINGLE (IEEE 754 32-bit) → 32 bits per value (8-bit exp, 24-bit mantissa)
  • DOUBLE (IEEE 754 64-bit) → 64 bits per value (11-bit exp, 53-bit mantissa) Default: SINGLE

Match this to your floating-point source precision.

In_IsTM In_IsTM

Determines if input is time-multiplexed:

  • NO → Input is scalar, broadcast to all TM phases
  • YES → Input is TM, phase-by-phase conversion Default: YES
Out_BitsInt Out_BitsInt

Number of integer bits in the fixed-point output. Range: 1-64. Default: 16.

Determines integer range:

  • Signed: [-2^(N-1), 2^(N-1) - 1]
  • Unsigned: [0, 2^N - 1]

Ensure sufficient bits to represent expected float values without overflow.

Out_BitsFract Out_BitsFract

Number of fractional bits in the fixed-point output. Range: 0-64. Default: 0.

Determines fractional resolution:

  • 0 bits → integer only
  • 8 bits → 1/256 resolution (~0.4%)
  • 16 bits → 1/65536 resolution (~0.0015%)

Example formats:

  • Q16.0 (16 int, 0 frac) → integers -32768 to 32767
  • Q8.8 (8 int, 8 frac) → -128.0 to 127.996
  • Q1.15 (1 int, 15 frac) → -1.0 to 0.99997
EnableSaturation EnableSaturation

Controls overflow behavior:

  • YES → Saturate at maximum/minimum representable value
  • NO → Wrap-around or undefined (modulo 2^N arithmetic) Default: YES.

Strongly recommended to enable for float-to-fixed conversion to prevent catastrophic errors when input values exceed output range.

TimeMultiplexing TimeMultiplexing
Time multiplexing factor (number of parallel conversions). Values: 4, 8, 16, 32. Default: 4. Determines how many independent conversions share the hardware.
PipelineLength PipelineLength
Number of pipeline stages in the converter. Range: 1-8. Default: 3. Higher values increase Fmax at the cost of latency. Total latency = PipelineLength × TM clock cycles.

Functional description

The component implements time-multiplexed float-to-fixed conversion:

$$ \text{OUT}[i] = \text{round}\left(\text{IN}[i] \times 2^{F_{\text{bits}}}\right), $$

where:

  • IN[i] → floating-point input (IEEE-754), phase $i$ (TM or scalar)
  • OUT[i] → fixed-point output, phase $i$ (always TM)
  • $F_{\text{bits}}$ → number of fractional bits in output format

The output format is configurable:

  • Integer bits (1-64)
  • Fractional bits (0-64)
  • Total width = Integer bits + Fractional bits

IEEE-754 Input Format

The input follows standard IEEE-754 encoding:

Single precision (32-bit):

  • 1 sign bit
  • 8 exponent bits (bias = 127)
  • 23 mantissa bits (24 with implicit leading 1)
  • Range: ±1.18×10⁻³⁸ to ±3.40×10³⁸

Double precision (64-bit):

  • 1 sign bit
  • 11 exponent bits (bias = 1023)
  • 52 mantissa bits (53 with implicit leading 1)
  • Range: ±2.23×10⁻³⁰⁸ to ±1.80×10³⁰⁸

Conversion Process

The float-to-fixed conversion involves:

  1. Sign extraction: Determine if value is negative
  2. Exponent processing: Extract and unbias exponent
  3. Mantissa alignment: Shift mantissa to align with fixed-point format
  4. Scaling: Multiply by $2^{F_{\text{bits}}}$ to get fixed-point integer
  5. Rounding: Round to nearest integer (ties to even)
  6. Saturation/wrapping: Handle overflow according to configuration
  7. Sign application: Apply sign if needed

Time Multiplexing

Time multiplexing processes multiple independent conversions through shared hardware:

Clock cycle Processing phase
0 Phase 0 → OUT[0] = fixed(IN[0])
1 Phase 1 → OUT[1] = fixed(IN[1])
… …
TM-1 Phase TM-1 → OUT[TM-1] = fixed(IN[TM-1])
TM Phase 0 (next cycle)

Scalar Broadcast Mode

When Input is TM = NO, a single floating-point value is broadcast to all output phases:

  OUT[0] = fixed(IN)
OUT[1] = fixed(IN)
...
OUT[TM-1] = fixed(IN)

This is useful for:

  • Broadcasting computed constants to all channels
  • Distributing calibration values
  • Test pattern generation

Overflow and Saturation

Overflow occurs when the floating-point value exceeds the fixed-point range:

For signed Q(N_int).(N_frac):

  • Maximum: $(2^{N_{\text{int}}-1} - 2^{-N_{\text{frac}}})$
  • Minimum: $-2^{N_{\text{int}}-1}$

For unsigned Q(N_int).(N_frac):

  • Maximum: $(2^{N_{\text{int}}} - 2^{-N_{\text{frac}}})$
  • Minimum: $0$

Enable Saturation property controls behavior:

  • YES → Saturate to max/min representable value
    • Prevents catastrophic errors
    • Recommended for signal processing
  • NO → Wrap around (modulo arithmetic)
    • Undefined behavior on overflow
    • Only for controlled environments

Special Value Handling

IEEE-754 Value Conversion Result
+0.0, -0.0 0 (zero)
+Infinity Max value (if saturated)
-Infinity Min value (if saturated)
NaN (Not a Number) 0 or undefined
Denormal Rounds to 0 or ±1

Precision Considerations

Precision loss can occur when:

  • Floating-point has more precision than fixed-point fractional bits
  • Example: Single precision (23-bit mantissa) → Q16.8 (8 frac bits): 15 bits lost

Quantization noise:

  • RMS quantization error ≈ $\frac{1}{\sqrt{12}} \times 2^{-N_{\text{frac}}}$
  • Example: 8 fractional bits → ~0.1% RMS error

Pipeline and Timing

The Pipeline Length property (1-8 stages) controls latency versus maximum clock frequency:

Pipeline Length Latency (clock cycles) Typical Fmax
1 TM × 1 300-350 MHz
2 TM × 2 400-450 MHz
3 TM × 3 500-550 MHz
4-8 TM × 4-8 550-600 MHz

Total latency = Pipeline Length × TM factor

Typical use cases

  • Converting FFT output to fixed-point for subsequent processing
  • Interface between floating-point algorithms and fixed-point DACs
  • Neural network inference output quantization
  • Post-processing of floating-point filter results
  • Mixed-precision computing pipelines
  • Preparing data for fixed-point hardware accelerators

Waveform example

Example with TM=4, Pipeline=3, scalar input with saturation:

If input value exceeds output range and saturation is enabled, OUT clamps to max/min.