Xilinx
Block Preview

Introduction

The block filters a continuous 16-bit stream by fast convolution: frames of $N$ samples (hop $N/2$, overlap-save) go through a forward FFT, are multiplied by the complex response $H[k]$ (Q15) and return through an inverse FFT; the first $N/2$ samples of each frame are discarded and the rest form the continuous filtered output. The equivalent FIR length is up to $N/2$ taps.

Double-click opens the FFT Filter Designer: Lowpass / Highpass / Bandpass / Bandstop presets with corner and transition controls, a Custom (draw) mode where the magnitude response is edited directly on the plot (click adds a point, drag moves it, double-click removes it), import of custom coefficients from file (h taps, one per line, or addr,re,im H bins) and CSV export of H[k] for the programmable variant. The plot overlays the target and the actual Q15-quantized response; the impulse response and the resource estimate are shown.

Pin Description

DATA_IN Input 16 bit BIT VECTOR
16-bit signed input stream, CE gated.
Default: Must be connected
CE Input 1 bit BIT
Clock enable, any duty up to 100%. Default ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
DATA_OUT Output 16 bit BIT VECTOR
Filtered 16-bit stream.
DV Output 1 bit BIT
Output sample valid.
BUSY Output 1 bit BIT
A frame is being processed.
OVERRUN Output 1 bit BIT
Reserved (always 0: the block sustains full rate).

Properties

Property window

FFT Length Length

FFT block size N (power of 2). Filter impulse response up to N/2 taps; latency ~2.5*N clocks.

FFT block size N (256..16384). Filter length up to N/2 taps; latency ~2.5 N.

Default: 1024

Options: 256 512 1024 2048 4096 8192 16384

Filter Filter

Filter summary (set by the designer, double-click)

Summary of the designed filter (set by the designer).

Default: Passthrough

Config (JSON, use designer) FFProject

Designer state incl. H[k] Q15 coefficients

Operation and constraints

  • Continuous stream, no START: filtering begins as soon as samples flow; the filter settles after ~N samples.
  • Full rate: the input can run at CE duty up to 100% (one sample per clock continuously). Two forward and two inverse xfft cores work in ping-pong; the useful halves of alternating frames come out exactly contiguous, so DV stays high without gaps in steady state.
  • Latency ~2.5 N clocks. Output 16 bit (inverse scaled by 1/N with rounding, saturated).
  • H[k] must be conjugate-symmetric for a real output - automatic with the designer (linear-phase design, h limited to N/2 taps with a Hann taper).

Verified in simulation at CE duty 100% (N=256, lowpass fc=0.1, broadband noise + two tones): gapless DV output matching the exact overlap-save reference at -79 dB rms (0.3 LSB); out-of-band tone rejected by 97 dB.

Runtime coefficients

Use FFT Filter Prog: same engine, H[k] in RAM loaded via COEF_ADDR / COEF_DATA / COEF_WE (addresses 0..N-1 = RE, N..2N-1 = IM, Q15; passthrough until loaded). Generate the file with the designer CSV export. Load while idle to avoid mixing responses inside one frame.