List

Busy – HIGH when the block is not accepting data.

This signal is HIGH when:

• Acquisition is disabled (CONFIG[0] = 0), OR
• FIFO is full

Logic: BUSY = NOT CONFIG[0] OR FULL

Use this signal to gate your data source when the List cannot accept more data.

Running – HIGH when acquisition is enabled via software.

Logic: RUNNING = CONFIG[0]

This signal directly mirrors the enable bit of the CONFIG register.

Clear – Outputs the internal reset signal.

Logic: CLEAR = CONFIG[1] OR RESET

Goes HIGH when either:

• Software reset is requested (CONFIG[1] = 1), OR
• Hardware RESET input is asserted

Use this signal to reset upstream logic when the List FIFO is cleared.

Data Input – Input data word to be written to the FIFO. Size is configurable (32 to 8192 bits).

Data is captured on the clock edge when WR is HIGH.

Write Enable – When HIGH (and acquisition is enabled), the value on IN is written to the FIFO on the clock edge.

If FIFO is full, data is lost.

Set the name of the endpoint

Default: List_0

Set the number of input to the virtual block

Default: 1

Options: 1 2 4 8 16 32 64 128

Size of the readout buffer. Buffer must be large enought to compensate readout bus stalls.

FIFO buffer depth in words. Available values: 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536.

Larger buffers compensate for readout bus stalls but use more FPGA resources. Default: 1024

Default: 1024

Options: 128 256 512 1024 2048 4096 8192 16384 32768 65536

Set the data word size in bits

Input data word size in bits. Available values: 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.

Larger words are converted to multiple 32-bit transfers internally. Default: 32

Default: 32

Options: 32 64 128 256 512 1024 2048 4096 8192

What the block writes to disk WHEN THE PROJECT IS SIMULATED (no effect on the synthesized design). None: the block does nothing, as it has always done. Single file: every word pushed into the list goes into one file, channel 0 first. Multi file per channel: one file per input. The files are written in the sim_results folder of the project, named after _. The list starts itself and is drained as fast as it fills, so no word is lost: in a simulation there is no software to start it or to read it out.

What the block writes to disk when the project is simulated. It has no effect on the synthesized design.

Files go to the project’s sim_results folder, named after <page>_<endpoint> plus _ch<n> in the multi-file mode. The exact paths are printed in the compiler log.

In a simulation nobody starts the list and nobody reads it out, so the block starts itself and is drained as fast as it fills: FULL stays low and no word is lost. There is no per event mode, because a list event is a single write — one file per event would mean one file per word.

Default: None

Default: None

Options: None Single file Multi file per channel

How the words are written. Binary - little endian (default): a raw byte stream, ceil(WordSize/8) bytes per word, least significant byte first. No header, no timestamp: feed it straight to a decoder. Extension .bin Binary - big endian: the same, most significant byte first. Hex text: one row per write, ‘<time_ns> …’, each word as WordSize/4 hex digits, most significant first. A nibble holding X/U is written as ‘X’. Extension .txt

How the words are written.

The binary formats are a bare stream — no header, no timestamp, no padding — so the file can be fed straight to a decoder. X/U bits are written as 0. The hex format is text, carries a header describing the columns and the ns timestamp of every write, and marks a nibble holding X/U as X rather than silently zeroing it.

Default: Binary - little endian

Default: Binary - little endian

Options: Binary - little endian Binary - big endian Hex text

Stop capturing after this many writes. The list free-runs in simulation, so this is what keeps a long run from filling the disk - one write costs Channels * WordSize/8 bytes. 0 means no limit.

Default: 4096