Block Preview

Introduction

Principle of Operation

The DT5560 has three SYNC output connectors on the front panel. Sync Out is the diagram-side handle on one of them: whatever bit you wire in appears on the connector, level for level, with no clock and no processing in between.

The block instance owns one connector, chosen with the Sync Pin property. To drive two connectors, place two blocks and give them different pins.

Its mirror image is Sync In, which reads the three separate SYNC input connectors. Inputs and outputs are distinct physical pins on the DT5560 - this is not a bidirectional port.

Pin Description

SYNC_0 Input 1 bit BIT

Level to drive onto the selected SYNC output connector.

The pin is named after the selected connector: with SyncPin = SYNC_1 the pin is called SYNC_1, and so on. RedesignIfChanged is set on the property, so changing the connector renames the pin and rebuilds the symbol - existing wires to the old pin name are not preserved.

Level sensitive and unregistered: the connector follows this bit for exactly as long as it is asserted.

The assignment is emitted unconditionally (no unconnected-pad guard), so wire it.

Default: Must be connected

Properties

Property window

Sync Pin SyncPin

Set sync pin to use for this block

Which of the three DT5560 SYNC output connectors this block drives. The choice determines the pin name, the pad name and the board signal.

Value Board signal Package pin
SYNC_0 SYNC_0_OUT C2
SYNC_1 SYNC_1_OUT B2
SYNC_2 SYNC_2_OUT A4

RedesignIfChanged is set - changing it rebuilds the symbol with a differently named pin. It can be changed after the block is created.

Default: SYNC_0

Default: SYNC_0

Options: SYNC_0 SYNC_1 SYNC_2

⚙️ Detailed Operation

What the block compiles to

The pin name, the pad name and the target signal all follow the Sync Pin property. For the default SYNC_0 the plug-in emits:

vhdl
  SYNC_0_OUT <= <your signal>;
  

It also prints one informational line into the compiler output:

Generating HDL code for <designator>

That is the whole block - no process, no generic, no register map entry, no SciSDK endpoint.

The board side

On the DT5560 the three targets are 1-bit vectors declared by the board’s top-level template, each with a defined idle value, and each wired to a real top-level port:

vhdl
  signal SYNC_0_OUT : std_logic_vector(0 downto 0) := "0";
signal SYNC_1_OUT : std_logic_vector(0 downto 0) := "0";
signal SYNC_2_OUT : std_logic_vector(0 downto 0) := "0";
...
SYNC_0_OUTb <= SYNC_0_OUT(0);
SYNC_1_OUTb <= SYNC_1_OUT(0);
SYNC_2_OUTb <= SYNC_2_OUT(0);
  

and constrained as single-ended 1.8 V CMOS outputs:

Sync Pin Board signal Top-level port Package pin I/O standard
SYNC_0 SYNC_0_OUT SYNC_0_OUTb C2 LVCMOS18
SYNC_1 SYNC_1_OUT SYNC_1_OUTb B2 LVCMOS18
SYNC_2 SYNC_2_OUT SYNC_2_OUTb A4 LVCMOS18

Because the signals carry an initial value of "0", a connector with no Sync Out block on it sits at logic low rather than floating.

Timing

Pure wiring: zero latency, no clock, no reset, no glitch filter. A combinational hazard on the driving signal reaches the connector. If the downstream instrument is edge sensitive, drive this block from a registered signal.

A one-clock pulse is as narrow as the connector’s electrical response allows

  • if the receiving device needs a wider pulse, stretch it in the diagram (for example with a Monostable) before this block.

Typical use

  • Exporting a trigger, gate or veto to another module or to a scope.
  • Daisy-chaining a run/stop or busy signal between DT5560 boards.
  • Marking an event of interest for external logging.

Board availability

DT5560 only. SupportedBoard is GUID_BASED with a single entry, C7F960A5-8051-45F0-B793-8899650BAB9D, which is the board GUID declared by the DT5560 board plug-in (boards/ni/board_DT5560/bDT5560.vb). The block does not appear in the toolbox on any other board, and no other board plug-in provides a SYNC_n_OUT signal for it to drive.

Note that the R5560 and R5560SE boards, despite the similar name, have input-only SYNC lines - see System Sync. There is no Sync Out equivalent there.