Xilinx
Block Preview

Introduction

Every CE clock the block outputs $\sqrt{-2\ln u}\cdot 2^{F}$: a Rayleigh distribution with mode $\sigma = 2^{F}$ LSB and mean $1.2533,\sigma$ – the envelope statistics of narrowband Gaussian noise (fading emulation, envelope detectors, magnitude of complex noise).

Rayleigh distribution

The histogram is measured on the bit-exact model the hardware is verified against (GHDL golden regression); the dashed line is the analytic Rayleigh PDF.

Pin Description

CE Input 1 bit BIT
Clock enable: one new sample per clock where high. Default: ‘1’.
Default: 1
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Restarts the sequence from the seed.
Default: Default Board Reset
OUT Output 16 bit BIT VECTOR
Rayleigh sample, UNSIGNED, OutputBits wide, saturated.
DV_OUT Output 1 bit BIT
High on every clock carrying a new sample.

Properties

Property window

Output bits OutputBits

Width of the OUT word (2..32), UNSIGNED, saturated.

Output width (2..32), unsigned, saturated.

Default: 16

Range: 2 – 32

Fract bits FractBits

Output Q format: OUT = sqrt(-2 ln u) * 2^FractBits. The distribution SIGMA is 2^FractBits LSB.

Output Q format (0..16): sigma of the distribution = 2^FractBits LSB.

Default: 12

Range: 0 – 16

SEED (32 digit hex) SEED

Seed of the embedded white generator (128 bit hex), expanded internally with SplitMix64. Auto-randomized when the component is created, so multiple instances produce independent noise; editable for reproducible runs. RESET restarts the sequence. Rayleigh distribution: OUT = sqrt(-2 ln u)*2^FractBits, unsigned, sigma = 2^FractBits LSB.

128-bit seed of the embedded white generator (auto-randomized at placement, editable).

Default: 4715C7A156E44655AAA709B64219BD7E

Usage

Latency 5 CE-clocks (DV marks valid outputs), throughput one sample per CE clock. The integer square root is exact (floor). RESET restarts the sequence; CE defaults to ‘1’.