Block Preview

Introduction

This block performs a programmable left shift operation on standard (non-TM) data streams. The shift amount is dynamically controlled via the integer SHIFT input port (0 to Max Shift).

The shift operation can be combinational (zero latency) or registered (1 clock cycle latency).

Pin Description

IN Input Variable bit BIT VECTOR
Input binary data (non-TM).
Default: Must be connected
SHIFT Input 1 bit INT
Shift amount control (integer, range 0 to Max Shift).
Default: Must be connected
CLK Input 1 bit BIT
Clock input (only when Latch Output = true).
Default: Default Board Clock
RESET Input 1 bit BIT
Reset input (only when Latch Output = true).
Default: Default Board Reset
OUT Output Variable bit BIT VECTOR
Left-shifted output

Properties

Property window

Input Size InputWordSize

Set the input word size in bits

Default: 32

Range: 2 – 16384

Max Shift Shift

Number of maximum bit to be shifted

Default: 16

Range: 1 – 64

Register Output LatchOutput

Select if latch the output. This will improve the performance but insert one clock cycle delay

  • false: Combinational output (0 latency)
  • true: Registered output (1 latency)

Default: True

InputWidth InputWidth
Number of bits per input sample. Range: 1 – 128.
MaxShift MaxShift
Maximum allowed shift amount. Range: 1 – 16.

Functional description

Implements a programmable barrel shifter (left shift) in VHDL.

$$ y = x \ll s $$

where $s$ is the shift amount from SHIFT input.

Latency modes

  • Latch Output = false: Combinational, latency = 0
  • Latch Output = true: Registered, latency = 1 clock cycle

Timing

Latency depends on Latch Output property: 0 or 1 clock cycles.