Xilinx
TM
Block Preview

Introduction

The block performs time-multiplexed addition across multiple data streams. On every rising edge of CLK, when A_DV = 1 and B_DV = 1, the adder computes

$$ \mathrm{OUT}_i(n) = \mathrm{A}_i(n) + \mathrm{B}_i(n), \quad i = 0, \ldots, \text{TM}-1, $$

where each subscript $i$ represents a different TM phase, and TM is the time-multiplexing factor (4, 8, 16, or 32).

Input A is always time-multiplexed. Input B can be either time-multiplexed (performing phase-by-phase addition) or scalar (broadcasting a single value to all phases).

The component leverages DSP48 slices for efficient hardware implementation with configurable pipeline stages (1-8) for optimal timing closure at high clock frequencies.

Pin Description

A Input Variable bit TM
Time-multiplexed input A (always TM). Width: (A Integer Bits + A Fractional Bits) × TM Factor. Contains TM phases packed sequentially: [A0, A1, …, A(TM-1)]. Each phase processes independently.
Default: Must be connected
A_DV Input 1 bit BIT
Data Valid for input A, active high. When high, input A contains valid data to be processed. Can be tied to ‘1’ for continuous streaming.
B Input Variable bit BIT VECTOR
Input B, can be time-multiplexed or scalar. If B is TM = YES: Width: (B Integer Bits + B Fractional Bits) × TM Factor Contains TM phases: [B0, B1, …, B(TM-1)] If B is TM = NO: Width: B Integer Bits + B Fractional Bits Single value broadcast to all TM phases
Default: Must be connected
B_DV Input 1 bit BIT
Data Valid for input B, active high. When high, input B contains valid data to be processed. Can be tied to ‘1’ for continuous streaming.
OUT Output 16 bit TM
Time-multiplexed output (always TM). Width: (OUT Integer Bits + OUT Fractional Bits) × TM Factor. Contains result phases: [OUT0, OUT1, …, OUT(TM-1)]. Valid when OUT_DV = 1.
OUT_DV Output 1 bit BIT
Data Valid output, active high. Indicates when OUT contains valid addition results. Asserts after Pipeline Length × TM clock cycles from input valid.
CLK
Global clock. Each rising edge processes one TM phase through the pipeline. Connected to system acquisition clock.
RESET
Synchronous reset, active high. Clears all pipeline registers and internal state.

Properties

Property window

A Integer Bits A_BitsInt

Number of integer bits for input A

Number of integer bits for input A. Range: 1-64. Determines the integer range of input A values.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

A Fractional Bits A_BitsFract

Number of fractional bits for input A

Number of fractional bits for input A. Range: 0-64. Determines the fractional precision of input A. Value interpretation: actual_value = integer_value / 2^(A_BitsFract)

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

A Sign A_Sign

Select if input A is signed or unsigned

Arithmetic type for input A:

  • UNSIGNED → Range: [0, 2^(total_bits) - 1]
  • SIGNED → Range: [-2^(total_bits-1), 2^(total_bits-1) - 1]

Default: SIGNED

Options: UNSIGNED SIGNED

B Integer Bits B_BitsInt

Number of integer bits for input B

Number of integer bits for input B. Range: 1-64. Determines the integer range of input B values.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

B Fractional Bits B_BitsFract

Number of fractional bits for input B

Number of fractional bits for input B. Range: 0-64. Determines the fractional precision of input B.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

B Sign B_Sign

Select if input B is signed or unsigned

Arithmetic type for input B:

  • UNSIGNED → Non-negative values only
  • SIGNED → Two’s complement representation

Default: SIGNED

Options: UNSIGNED SIGNED

B is TM B_IsTM

Select if input B is Time Multiplexed or scalar

Determines if input B is time-multiplexed:

  • NO → B is scalar, broadcast to all TM phases
  • YES → B is TM, phase-by-phase addition with A

Default: NO

Options: NO YES

OUT Integer Bits Out_BitsInt

Number of integer bits for output

Number of integer bits for output. Range: 1-64. Should be ≥ max(A_BitsInt, B_BitsInt) + 1 for full range without overflow.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

OUT Fractional Bits Out_BitsFract

Number of fractional bits for output

Number of fractional bits for output. Range: 0-64. Typically set to max(A_BitsFract, B_BitsFract) to preserve precision.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

OUT Sign Out_Sign

Select if output is signed or unsigned

Arithmetic type for output:

  • UNSIGNED → Output range [0, 2^N - 1]
  • SIGNED → Output range [-2^(N-1), 2^(N-1) - 1]

Default: SIGNED

Options: UNSIGNED SIGNED

TM Factor TimeMultiplexing

Time Multiplexing factor

Time multiplexing factor (number of parallel phases). Values: 4, 8, 16, 32. Determines how many independent data streams are processed through the same hardware operator.

Default: 4

Options: 4 8 16 32

Pipeline Length PipelineLength

Number of pipeline stages (1-8)

Number of pipeline stages in the adder datapath. Range: 1-8. Higher values increase Fmax at the cost of latency. Total latency = PipelineLength × TM clock cycles.

Default: 3

Options: 1 2 3 4 5 6 7 8

Enable Saturation EnableSaturation

Enable output saturation (otherwise overflow)

Controls overflow behavior:

  • YES → Saturate at maximum/minimum representable value
  • NO → Wrap-around (modulo 2^N arithmetic)

Saturation is recommended for signal processing to avoid large errors.

Default: YES

Options: NO YES

Functional description

The component implements a time-multiplexed adder supporting independent fixed-point formats for each input:

$$ \text{OUT}[i] = A[i] + B \quad \text{or} \quad \text{OUT}[i] = A[i] + B[i], $$

where:

  • A[i] → input A, phase $i$ (always TM)
  • B or B[i] → input B, scalar or TM phase $i$
  • OUT[i] → output, phase $i$ (always TM)

Each input has independently configurable:

  • Integer bits (1-64)
  • Fractional bits (0-64)
  • Sign mode (SIGNED/UNSIGNED)

The output format is also independently configurable, allowing for headroom to prevent overflow or precision adjustment.

Time Multiplexing

Time multiplexing allows processing multiple data streams through a single hardware operator by cycling through different phases on consecutive clock cycles:

Clock cycle Processing phase
0 Phase 0 → OUT[0] = A[0] + B[0]
1 Phase 1 → OUT[1] = A[1] + B[1]
… …
TM-1 Phase TM-1 → OUT[TM-1] = A[TM-1] + B[TM-1]
TM Phase 0 (next cycle)

Scalar Broadcast Mode

When B is TM = NO, input B is broadcast to all TM phases:

  OUT[0] = A[0] + B
OUT[1] = A[1] + B
...
OUT[TM-1] = A[TM-1] + B

This is useful for adding a constant offset or bias to all channels.

Overflow Handling

The Enable Saturation property controls overflow behavior:

  • YES → Output saturates at maximum/minimum representable value
  • NO → Output wraps around (modulo arithmetic)

Mathematical background

In fixed-point arithmetic with $N_{\text{int}}$ integer bits and $N_{\text{frac}}$ fractional bits, values represent:

$$ \text{value} = \frac{\text{integer representation}}{2^{N_{\text{frac}}}} $$

For addition, the integer representations are summed and the result is scaled to the output format.

Pipeline and Timing

The Pipeline Length property (1-8 stages) controls latency versus maximum clock frequency:

Pipeline Length Latency (clock cycles) Typical Fmax improvement
1 TM × 1 Baseline
2 TM × 2 +20%
3 TM × 3 +35%
4 TM × 4 +45%
8 TM × 8 +60%

Total latency = Pipeline Length × TM factor

DSP Slice Utilization

The component targets Xilinx DSP48 slices for efficient implementation. Each DSP slice can perform one addition per clock cycle, making it ideal for high-throughput TM designs.

Typical use cases

  • Multi-channel signal processing (audio, video, communications)
  • Parallel filter banks with multiple channels
  • MIMO systems requiring simultaneous processing of multiple streams
  • Resource-efficient high-throughput arithmetic where multiple operations share hardware
  • Bias addition in neural network accelerators

Waveform example

Example with TM=4, Pipeline=3, B is scalar: