RF Complex DC Blocker (IIR HP)

Introduction link

The Complex DC Blocker (IIR HP) applies the classic first-order DC-block difference equation to each channel independently:

      y[n] = x[n] - x[n-1] + alpha * y[n-1]
  

Its transfer function is

      H(z) = (1 - z^-1) / (1 - alpha * z^-1)
  

a zero at DC (z = 1) that nulls the mean, and a pole at z = alpha just inside it that sets how sharply the notch tapers. With alpha close to 1 the high-pass cutoff is very low, so only DC and the slowest drift are removed and the rest of the signal passes essentially untouched.

The approximate 3 dB cutoff is

      f_c / Fs ~= (1 - alpha) / (2*pi)
  

so e.g. alpha = 0.99 at Fs = 100 MHz gives a cutoff near 160 kHz.

Pin Description link

Properties link

Usage link

Stateful / feedback behaviour link

This is an IIR / stateful filter. The C++ core keeps static feedback registers per channel that carry the previous input and previous output:

      static in_t  x_prev_i, x_prev_q;   // x[n-1]
    static out_t y_prev_i, y_prev_q;   // y[n-1]  (the recursive feedback)
  

Each clock it forms y[n] = x[n] - x[n-1] + (alpha * y[n-1]) in a wide accumulator, truncates to the output word, and stores it back as y_prev for the next sample. The I and Q channels use identical, independent filters (same alpha).

Alpha and the fixed-point shift link

alpha is chosen from the property list (0.90 .. 0.9995) and converted by the plugin to a fixed-point numerator:

      alpha_num = round(alpha * 2^15)      (ALPHA_SHIFT = 15)
  

The feedback term is computed as an integer multiply followed by a right shift that undoes the scaling, applied to the MAGNITUDE of the product so that the division truncates towards zero:

      alpha * y[n-1]  ->  sign(p) * (|p| >> 15),   p = alpha_num * y_prev
  

So alpha_num / 32768 is the effective coefficient (e.g. 0.99 becomes 32440 / 32768). The >> 15 rescaling is the load-bearing operation: it keeps the recursive product at the same scale as the samples. Truncating towards zero makes the feedback an odd function of the state, so the two signs behave identically and every transient reaches exactly 0; a plain arithmetic shift would round towards minus infinity and leave a permanent negative residue (any state in [-99, 0] would be a fixed point at alpha = 0.99) on each channel independently, i.e. a standing I/Q offset. Alpha closer to 1 = lower cutoff = slower DC tracking but a narrower notch.

Bit widths link

Data is signed two’s complement.

• IN_I, IN_Q : signed InputSize bits.
• OUT_I, OUT_Q : signed InputSize + 1 bits (one guard bit for the x[n] - x[n-1] difference).
• internal accumulator : OutputSize + ALPHA_SHIFT + 2 bits, wide enough to hold the pre-shift feedback product without overflow.

Reset behaviour link

RESET is the HLS synchronous reset (ap_rst). On assertion the feedback registers x_prev and y_prev clear to zero. Because the filter is recursive, after reset (or a large step) the output shows a decaying transient that settles with a time constant of roughly 1 / (1 - alpha) samples before the DC notch is fully established.

Latency and throughput link

• #pragma HLS PIPELINE II=1 : one sample pair per clock.
• 1-clock latency.
• All ports use ap_none.
• #pragma HLS INTERFACE ap_ctrl_none port=return : no block-level control.

Typical applications link

• DC / LO-leakage removal on a down-converted baseband stream.
• ADC offset / bias cancellation without a big FIR.
• Drift / baseline-wander suppression ahead of a detector.

Resources & Timing link

• Latency: 1 clock cycle

• Throughput: 1 sample per clock (II=1)

One multiplier per channel for the feedback term plus a couple of adders; the »15 shift rescales the recursive product. No BRAM. IIR / stateful (static x[n-1] and y[n-1] feedback registers). After reset or a step the output settles with time constant ~1/(1-alpha) samples.