Block Preview

Introduction

This block implements a rising edge detector that generates output pulses whenever an input signal transitions from ‘0’ to ‘1’ (low-to-high).

The edge detector operates as follows:

  • Monitors input signal(s) for 0→1 transitions
  • Generates a pulse on OUT for each detected rising edge
  • Pulse width is configurable (default: 1 clock cycle)
  • Each bit in multi-bit inputs has an independent edge detector

Key characteristics:

  • Edge-triggered: Responds only to 0→1 transitions
  • Multi-bit: Processes up to 128 independent signals
  • Pulse generation: Creates clean, synchronous pulses
  • Configurable width: Pulse duration from 1 to N clock cycles
  • Latency: 2 clock cycles

Pin Description

IN Input Variable bit BIT
Input signal(s) to monitor for rising edges. Width: Configurable via Input bits property (1-128 bits). Each bit has an independent edge detector. Transitions from ‘0’ to ‘1’ are detected and generate output pulses.
Default: Must be connected
CE Input 1 bit BIT

Clock Enable input (active high).

  • CE = ‘1’: Edge detection enabled
  • CE = ‘0’: Edge detection disabled (input changes ignored) Default: ‘1’ if left unconnected.
Default: 1
CLK Input 1 bit BIT
Clock input signal. Edge detection operates synchronously with this clock. Automatically connected to global clock if left unconnected.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset signal (active high). Clears internal state and stops any ongoing pulses. Automatically connected to global reset if left unconnected.
Default: Default Board Reset
PULSE_WIDTH Input 1 bit INT

Pulse width in clock cycles (integer). Determines how many cycles the output pulse remains high after edge detection.

  • PULSE_WIDTH = 1: Single-cycle pulse
  • PULSE_WIDTH = N: N-cycle pulse Default: 1 if left unconnected.
OUT Output Variable bit BIT
Edge detection output pulses. Width: Same as IN (Input bits property). OUT[i] = ‘1’ for PULSE_WIDTH cycles after IN[i] rising edge. Latency: 2 clock cycles from input edge to output pulse.

Properties

Property window

Input bits InputSize

Set the number of bits of the input signal. For each bit will be created an indipendent edge detector

Number of independent edge detectors (width of IN and OUT). Range: 1-128 bits. Each bit has its own edge detector operating in parallel.

Default: 1

Range: 1 – 128

Functional description

A rising edge detector identifies low-to-high transitions on input signals and generates synchronized output pulses. Each bit of the input has its own independent edge detection circuit.

Operation principle

For each input bit $i$:

$$ \mathrm{Edge}[i] = \mathrm{IN}i \land \overline{\mathrm{IN}i} $$

Where:

  • $\mathrm{IN}i$ = current value of bit $i$
  • $\mathrm{IN}i$ = previous value of bit $i$ (1 clock ago)
  • $\land$ = logical AND
  • $\overline{x}$ = logical NOT

A rising edge is detected when:

  • Previous cycle: IN[i] = ‘0’
  • Current cycle: IN[i] = ‘1’

Pulse generation

When a rising edge is detected:

  • Output bit goes HIGH for PULSE_WIDTH clock cycles
  • After PULSE_WIDTH cycles, output returns to LOW
  • New edges can be detected after the pulse completes

Multi-bit operation

The component processes each input bit independently:

  • Input Size = 8 → 8 independent edge detectors
  • Each detector operates on its corresponding bit
  • Edges on different bits are detected simultaneously
  • OUT[i] reflects edge detection for IN[i]

Pulse width control

The PULSE_WIDTH input (integer) determines pulse duration:

  • PULSE_WIDTH = 1: Single-cycle pulse (default)
  • PULSE_WIDTH = N: N-cycle pulse
  • Useful for generating enable signals of specific durations

Clock enable

The CE input enables/disables edge detection:

  • CE = ‘1’: Edge detection active
  • CE = ‘0’: Edges are not detected (input changes ignored)

Timing

Property Latency (clock cycles)
Rising Edge Detector 2

The output pulse appears 2 clock cycles after the rising edge occurs on the input.

Timing diagram 

  Cycle:     0    1    2    3    4    5    6
CLK:       ↑    ↑    ↑    ↑    ↑    ↑    ↑
IN:        0    1    1    0    1    1    1
OUT:       0    0    1    0    0    1    0
             (edge)    (pulse)    (edge)    (pulse)

Note: 2-cycle latency from edge to pulse.

Typical use cases

  • Asynchronous input synchronization: Convert async signals to sync pulses
  • Button debouncing: Detect button presses (combine with debouncer)
  • Event counting: Count rising edge events
  • Trigger generation: Create enable pulses from control signals
  • Interrupt detection: Generate interrupts on signal transitions
  • Protocol handshaking: Detect ready/acknowledge edges
  • Clock domain crossing: Synchronize signals between domains
  • Strobe generation: Create single-cycle strobes from level signals

Design best practices

  1. Metastability: For async inputs, use a synchronizer chain before edge detector
  2. Glitch filtering: Ensure input signal is stable (debounce if necessary)
  3. Pulse width: Choose PULSE_WIDTH appropriate for downstream logic
  4. Latency: Account for 2-cycle detection delay in timing analysis
  5. Reset: Initialize properly to avoid false edges on power-up

Waveform example

Example with Input Size = 2, PULSE_WIDTH = 1 (single-cycle pulses):

Note: Each rising edge generates a 1-cycle pulse after 2-cycle latency.

Example with PULSE_WIDTH = 3 (three-cycle pulses):

Pulse extends for 3 clock cycles.