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Introduction

This block generates a constant integer value using the VHDL INTEGER type. Unlike bit-vector constants, integers are treated as mathematical values rather than binary patterns, making them ideal for:

  • Loop counters and array indices
  • Generic parameters and size calculations
  • Arithmetic operations requiring signed integer math
  • Control logic and state machine values

The component accepts values in multiple formats:

  • Hexadecimal: 0xFF, 0x1000, 0xDEAD
  • Binary: 0b10101010, 0b11110000
  • Decimal: 255, -1024, 3735928559

The output is a VHDL INTEGER type (32-bit signed, range: -2,147,483,648 to 2,147,483,647) with zero clock latency.

Pin Description

CONST Output 1 (INTEGER type, not bit-vector) bit INT

Constant integer output in VHDL INTEGER type (32-bit signed), always combinational (zero latency). Width: Fixed at 32 bits (VHDL INTEGER standard).

The output value is fixed at design time and remains constant during operation. Suitable for direct use in integer arithmetic or as generic parameters in VHDL generate statements.

Properties

Property window

Value Value

Set the value of the constant. Use 0x for exadecimal Use 0b for binary code

Constant integer value in hexadecimal (0x…), binary (0b…), or decimal format. Examples: 0xFF (255), 0b10101010 (170), 1000, -50. Must fit in 32-bit signed range: -2,147,483,648 to 2,147,483,647.

Default: 0

Functional description

The component implements a constant integer source in VHDL. The value is defined at compile time and hardwired into the design:

$$ \mathrm{CONST} = V $$

where $V$ is the user-specified integer constant value.

VHDL INTEGER type

The output uses the VHDL INTEGER type, which is:

  • Signed 32-bit integer
  • Range: $-2^{31}$ to $2^{31}-1$ (-2,147,483,648 to 2,147,483,647)
  • Synthesis: Typically mapped to 32-bit std_logic_vector with sign extension

This differs from std_logic_vector constants, which are unsigned bit patterns. Use INTEGER when you need:

  • Negative values with automatic sign handling
  • Arithmetic operations (+, -, *, /) without manual type conversions
  • Loop indices or array sizes in VHDL generate statements

Value formats

The component supports three input formats:

  • Hexadecimal (0x prefix): Compact notation for large values

      Value: 0xFF        → Integer: 255
Value: 0x1000      → Integer: 4096
Value: 0xFFFFFFFF  → Integer: 4294967295 (converted to signed)

  • Binary (0b prefix): Explicit bit pattern specification

      Value: 0b10101010  → Integer: 170
Value: 0b11110000  → Integer: 240

  • Decimal (no prefix): Standard integer notation

      Value: 255         → Integer: 255
Value: -1024       → Integer: -1024 (negative values supported)
Value: 1000000     → Integer: 1000000

Signed vs. unsigned interpretation

When using hexadecimal or binary notation, the component interprets values as unsigned during parsing, then converts to signed INTEGER:

  Value: 0xFFFFFFFF (unsigned: 4,294,967,295)
INTEGER result: -1 (signed 32-bit interpretation)

For negative constants, use decimal notation:

  Value: -100        → INTEGER: -100 (explicit negative)

Range limits

Values must fit within the 32-bit signed INTEGER range. Overflow behavior:

  • Values > 2,147,483,647: Wrapped to negative (two’s complement)
  • Values < -2,147,483,648: Compilation error or unpredictable behavior

For values outside this range, use a bit-vector constant instead.

Implementation details

The VHDL implementation declares a signal and assigns the constant:

vhdl 
  signal CONST : INTEGER := 0;
CONST <= <parsed_value>;

Depending on the input format:

  • Hexadecimal: Parsed with Convert.ToUInt32(value, 16)
  • Binary: Parsed with Convert.ToUInt32(value, 2)
  • Decimal: Used directly as integer literal

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Constant Integer 0

The output is available immediately after FPGA configuration and does not depend on any clock signal.

Typical use cases

  • Generic parameters: Define configurable design sizes (e.g., FIFO depth, data width)
  • Loop counters: Provide constant iteration counts in for loops
  • Array indices: Supply fixed addresses or offsets for memory/register access
  • Arithmetic constants: Multipliers, divisors, or offsets in integer math
  • State machine values: Define enumeration-like constants for FSM states
  • Control thresholds: Comparison values for counters or threshold detectors
  • Timeout values: Fixed delay counts for timers and watchdogs

Example configurations

Example 1: Loop counter maximum 

  Value: 1000
Use case: Maximum count for a loop or counter
Output: INTEGER = 1000

Example 2: Memory address offset 

  Value: 0x1000
Use case: Base address for memory-mapped registers
Output: INTEGER = 4096

Example 3: Negative offset 

  Value: -50
Use case: Signed offset for centering or calibration
Output: INTEGER = -50

Example 4: Binary mask size 

  Value: 0b1111
Use case: 4-bit mask or size parameter
Output: INTEGER = 15

INTEGER vs. BIT-VECTOR constants

Feature INTEGER Constant Bit-Vector Constant
Type Signed 32-bit Unsigned N-bit
Width Fixed 32 bits Configurable
Negative values Native support Requires 2’s comp
Arithmetic Direct (+, -, *) Needs conversion
Bit manipulation Limited Full bitwise ops
Use case Math, indices Masks, patterns

Choose INTEGER for mathematical values and BIT-VECTOR for bit patterns.