Sequential Logic blocks
Bit-Array Synchronizer (CCCC)
Clock Crossing Chain Component for safe multi-bit synchronization between asynchronous clock …
Both Edge Detector
Dual-edge detector that generates single-cycle pulses when input signals transition in either …
D Flip-Flop (Falling Edge)
Falling-edge-triggered D-type flip-flop for synchronous data storage. Samples multi-bit input data …
D Flip-Flop (Rising Edge)
Rising-edge-triggered D-type flip-flop for reliable synchronous data storage. Samples multi-bit …
D Latch
Level-sensitive transparent latch that stores multi-bit data values. When the clock enable signal is …
D Latch [TM]
Time-multiplexed D-type latch for storing multiple parallel data streams. Level-sensitive …
Falling Edge Detector
Falling edge detector that generates single-cycle pulses when input signals transition from high to …
Monostable (Pulse Shaper)
Monostable multivibrator (one-shot) that generates fixed-width output pulses in response to input …
Rising Edge Detector
Rising edge detector that generates single-cycle pulses when input signals transition from low to …
SR Flip-Flop
Set-Reset flip-flop (SR latch) for bistable storage without clock-dependent data input. Provides …
SR Flip-Flop (Clocked)
Clocked Set-Reset flip-flop for synchronous bistable storage with explicit clock input. Provides …
Synchronizer (Legacy)
Legacy Xilinx-only synchronizer for multi-bit clock domain crossing. Provides single-stage …