MISC blocks
Binary To Integer
Converts a std_logic_vector binary signal to a VHDL INTEGER type. The component translates a …
Constant Bit (True/False)
Generates a constant single-bit value representing boolean True (1) or False (0). Provides a simple …
Constant Bit (True/False) [TM]
Time-multiplexed constant single-bit source. Generates boolean True (1) or False (0) values across …
Constant Bit-Vector
Generates a constant bit-vector value with configurable width. Supports hexadecimal (0x…), binary …
Constant Bit-Vector [TM]
Time-multiplexed constant bit-vector source. Generates fixed bit-vector values across multiple TM …
Constant Fixed-Point
Generates a constant fixed-point value with configurable integer and fractional bit widths. Converts …
Constant Fixed-Point [TM]
Time-multiplexed constant fixed-point source. Generates fixed-point values across multiple TM phases …
Constant Floating-Point
Generates a constant floating-point value compliant with IEEE-754 standard. Supports both …
Constant Floating-Point [TM]
Time-multiplexed constant floating-point source compliant with IEEE-754. Generates floating-point …
Constant Integer
Generates a constant integer value in VHDL INTEGER type (32-bit signed). Supports hexadecimal …
Constant Time
Generates a constant time value converted to clock cycles based on system frequency. Supports …
Custom HDL (NEW)
Advanced HDL editor with Monaco Editor, multi-file support, generics, GHDL syntax checking, and …
Integer To Binary
Converts a VHDL INTEGER type signal to a std_logic_vector binary representation. The component …
Polarity Invert
Switchable polarity inverter for a single data stream. A one-bit control pin chooses between …
Polarity Invert (TM)
Time-multiplexed polarity inverter: the same switchable inversion as the scalar Polarity Invert, …
Signed/Unsigned Converter
Converts between signed and unsigned binary representations with configurable bit width scaling. …
Signed/Unsigned Converter [TM]
Time-multiplexed version of the signed/unsigned converter. Converts between signed and unsigned …
STD Logic Vector / TM Converter
Flexible bidirectional converter between std_logic_vector and time-multiplexed (TM) signal formats. …
TM Packer
Packs multiple independent std_logic_vector signals into a single time-multiplexed (TM) bus. Takes N …
TM Phase Extractor
Extracts a single specific phase from a time-multiplexed (TM) bus and outputs it as a scalar …
TM Signal Replicator
Replicates a single scalar std_logic_vector signal to all phases of a time-multiplexed (TM) bus. …
TM Splitter
Splits a single time-multiplexed (TM) bus into multiple independent std_logic_vector signals. Takes …
User HDL
The original custom-HDL block: one VHDL entity, typed into a built-in editor and stored inside the …
User HDL Link
Link to external HDL files folder without embedding code in the project. Supports GHDL syntax …