Memory

Deserializer (Serial to Parallel)

Converts serial bit stream to parallel data. Shifts in bits from SERIAL_IN one per clock cycle while …

FIFO (Altera/Intel)

First-In-First-Out queue optimized for Intel (Altera) FPGAs. Functionally identical to FIFO_XLX but …

FIFO (First-In-First-Out)

First-In-First-Out queue with independent read and write clocks. Buffers data between asynchronous …

FIFO [TM]

Time-multiplexed FIFO buffer for TM data streams. Processes multiple TM phases through a shared …

Fixed Delay

Synchronous fixed delay line that delays the input signal by a user-configured number of clock …

Fixed Delay [TM]

Time-multiplexed fixed delay line that delays TM input signals by a user-configured number of clock …

Gate and Delay (SW)

Programmable gate and delay block that delays an input pulse and stretches its width. The DELAY …

RAM Dual Port

Simple dual-port RAM with independent read and write ports. Allows simultaneous read and write …

RAM Single Port

Single-port Random Access Memory with configurable depth and width. Provides read and write …

ROM (Read-Only Memory)

Read-only memory initialized from user-provided data file. Stores constant data that cannot be …

Serializer (Parallel to Serial)

Converts parallel data to serial bit stream. Loads parallel DATA when LE=1, then shifts out bits one …

Single Clock Delay

Single-cycle register delay element. Delays input signal by exactly one clock cycle with …

Single Clock Delay [TM]

Time-multiplexed single-cycle register delay. Delays each TM phase by exactly one clock cycle with …

Variable Delay (Programmable)

Programmable delay line with runtime-adjustable delay controlled by the DELAY input. Uses FPGA block …

Variable Delay Fine [TM]

Advanced time-multiplexed programmable delay with sample-level precision. Unlike group TM delay, …

Variable Delay Group [TM]

Time-multiplexed programmable delay line with runtime-adjustable delay for all TM phases. All phases …